A few things about the circuit:
It is an ok topology if you do not have a bipolar transistor where the collector only connects to a supply (ground here). By putting the amplifier across the delta_Vbe you create an offset which is gained up something like 10x to the bandgap (54mV to 500mV-ish). To make matters worse, the offset is not PTAT. Thus if you trim it out using the PTAT trim you will have a bandgap that looks great at 25C but has attrocious temperature drift.
If you do have the abillity to tie the collectors to another node consider a gained up brokaw cell. It is easy and performs much better.
As someone else mentioned the capacitor location is problematic. One end is to the bandgap and the other is to 1 diode below the power supply. That will wreck your PSRR. Nearly identical (possibly better) stability can be achieved by instead tying it between Vbg and the cascode node 1 NMOS down from the node it is tied to now. It is still a miller cap when tied that way. The RHP zero is pushed out dramatically though because that cascode node is relatively low impedance. Also that node is ground referenced so that ripple on the power supply will not automatically exist there.
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发表于 2020-7-5 05:54:51
