职位要求
[color=rgba(0, 0, 0, 0.6)]15+ years (minimum 12 years) of ASIC verification work experience.
Experience of UVM based verification flow
Experience as technical lead on asic verification.
Experience with assertion, function coverage driven methodology.
Experience or knowledge of AXI/APB/AHB bus protocol.
Familiar with SystemVerilog and UVM methodology.
Deep understanding on PCIe protocol/datapath.
Self-motivated, good communication with other team members.
Experience of CCIX/CXL protocol is a big plus.
Experience with ARM based C/Assembly test development is a plus.