Verilog FSM testbench

cityblues

我在網上找了一個FSM的testbench跟code但是我怎麼樣complie testbench都
沒能顯示出FSM裡的每個state之類的
有人知道怎麼做嗎?

============================================
以下是testbench
=============================================================
`timescale 1ns / 1ps
// fpga4student.com: FPGA projects, Verilog projects, VHDL projects
// Verilog project: Verilog code for Sequence Detector using Moore FSM
// Verilog Testbench for Sequence Detector using Moore FSM
module tb_Sequence_Detector_Moore_FSM_Verilog;
// Inputs
reg sequence_in;
reg clock;
reg reset;
// Outputs
wire detector_out;
// Instantiate the Sequence Detector using Moore FSM
Sequence_Detector_MOORE_Verilog uut (
  .sequence_in(sequence_in),
  .clock(clock),
  .reset(reset),
  .detector_out(detector_out)
);
initial begin
clock = 0;
forever #5 clock=~clock;
end


initial begin
  // Initialize Inputs
  sequence_in = 0;
  reset = 1;
  // Wait 100 ns for global reset to finish
  #30;
      reset = 0;
  #40;
  sequence_in = 1;
  #10;
  sequence_in = 0;
  #10;
  sequence_in = 1;
  #20;
  sequence_in = 0;
  #20;
  sequence_in = 1;
  #20;
  sequence_in = 0;  
  // Add stimulus here
end
endmodule


========================================================================================
以下是code
=======================================================
// fpga4student.com: FPGA projects, Verilog projects, VHDL projects
// Verilog project: Verilog code for Sequence Detector using Moore FSM
// The sequence being detected is "1011" or One Zero One One
module Sequence_Detector_MOORE_Verilog(sequence_in,clock,reset,detector_out);
input clock; // clock signal
input reset; // reset input
input sequence_in; // binary input
output reg detector_out; // output of the sequence detector
parameter  Zero=3'b000, // "Zero" State
    One=3'b001, // "One" State
    OneZero=3'b011, // "OneZero" State
    OneZeroOne=3'b010, // "OnceZeroOne" State
    OneZeroOneOne=3'b110;// "OneZeroOneOne" State
reg [2:0] current_state, next_state; // current state and next state
// sequential memory of the Moore FSM
always @(posedge clock, posedge reset)
begin
if(reset==1)
current_state <= Zero;// when reset=1, reset the state of the FSM to "Zero" State
else
current_state <= next_state; // otherwise, next state
end
// combinational logic of the Moore FSM
// to determine next state
always @(current_state,sequence_in)
begin
case(current_state)
Zero:begin
  if(sequence_in==1)
   next_state <= One;
  else
   next_state <= Zero;
end
One:begin
  if(sequence_in==0)
   next_state <= OneZero;
  else
   next_state <= One;
end
OneZero:begin
  if(sequence_in==0)
   next_state <= Zero;
  else
   next_state <= OneZeroOne;
end
OneZeroOne:begin
  if(sequence_in==0)
   next_state <= OneZero;
  else
   next_state <= OneZeroOneOne;
end
OneZeroOneOne:begin
  if(sequence_in==0)
   next_state <= OneZero;
  else
   next_state <= One;
end
default:next_state <= Zero;
endcase
end
// combinational logic to determine the output
// of the Moore FSM, output only depends on current state
always @(current_state)
begin
case(current_state)
Zero:   detector_out <= 0;
One:   detector_out <= 0;
OneZero:  detector_out <= 0;
OneZeroOne:  detector_out <= 0;
OneZeroOneOne:  detector_out <= 1;
default:  detector_out <= 0;
endcase
end
endmodule


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ayamitek

thanks for sharing

cityblues

所以有人知道怎麼模擬FSM嘛