想问一下关于理想ADC中的verlogA语言问题

BRC000

  最近在做DAC，仿真需要用到理想ADC，我在论坛里找了个verlogA的教程，模仿里面的例子写了一个理想ADC，但是我写的代码生成的ADC不能设定采样频率，想问一下怎么改代码才可以自己设定理想ADC的采样频率。
  以下是我的代码
// verilogA for 000, BITS16, veriloga

`include "constants.vams"
`include "disciplines.vams"


` define BITS 16
module adc(in, out) ;
input in ;
output [0: ` BITS - 1] out ;
electrical in;
electrical [0: ` BITS - 1] out ;
parameter fullscale = 1.2, tdelay = 0 ,trantime = 0;
real samp, half ;
Analog begin
half = fullscale/2.0 ;
samp = V(in) ;
V(out[15]) <+ transition(samp > half, tdelay, trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
V(out[14]) <+ transition(samp > half, tdelay,trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
V(out[13]) <+ transition(samp > half, tdelay, trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
V(out[12]) <+ transition(samp > half, tdelay, trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
V(out[11]) <+ transition(samp > half, tdelay, trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
V(out[10]) <+ transition(samp > half, tdelay, trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
V(out[9]) <+ transition(samp > half, tdelay, trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
V(out[8]) <+ transition(samp > half, tdelay, trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
V(out[7]) <+ transition(samp > half, tdelay, trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
V(out[6]) <+ transition(samp > half, tdelay, trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
V(out[5]) <+ transition(samp > half, tdelay, trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
V(out[4]) <+ transition(samp > half, tdelay, trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
V(out[3]) <+ transition(samp > half, tdelay, trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
V(out[2]) <+ transition(samp > half, tdelay, trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
V(out[1]) <+ transition(samp > half, tdelay, trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
V(out[0]) <+ transition(samp > half, tdelay,trantime);
if (samp > half) samp = samp - half ;
samp = 2.0 * samp ;
end
endmodule

Littleoil

input 沒有宣告 clock進來宣告完之後可以調用 cross function 來得到你想要的結果

Frappuccino

问，楼主成功了吗？