icc

殷盛霖

icc进行读取网表时报错
c_shell> import_designs -format verilog -top $top_design -cel $top_design {/home/train/y_chengxuexiao/icc/lab1_data_setup/design_data/RISC_CHIP.v}
Loading db file '/home/EDA/synopsys/icc_2016/libraries/syn/gtech.db'
Loading db file '/home/EDA/synopsys/icc_2016/libraries/syn/standard.sldb'

*****  Verilog HDL translation! *****

*****    Start Pass 1 *****
Compiling source file /home/train/y_chengxuexiao/icc/lab1_data_setup/design_data/RISC_CHIP.v

*****  Pass 1 Complete *****
Elapsed =    0:00:00, CPU =    0:00:00

*****  Verilog HDL translation! *****

*****    Start Pass 2 *****
Compiling source file /home/train/y_chengxuexiao/icc/lab1_data_setup/design_data/RISC_CHIP.v
Error:   /home/train/y_chengxuexiao/icc/lab1_data_setup/design_data/RISC_CHIP.v:12:  module ad01d0 is not defined.
(VER-500)
Error: Module 'ad01d0' is not defined.  (MWNL-297)
Error:   /home/train/y_chengxuexiao/icc/lab1_data_setup/design_data/RISC_CHIP.v:12: ERROR: near line 12: Port connection failed.
(VER-500)

Error: Verilog parser cannot parse the /home/train/y_chengxuexiao/icc/lab1_data_setup/design_data/RISC_CHIP.v source file. (MWNL-047)
Error: Current design is not defined. (UID-4)