为什么说我的if后面缺endmodule

zleewin

module filter(
input signed[7:0] rg1,
input signed[7:0] rg2,
input signed[7:0] rg3,
input signed[7:0] rg4,
input wire sel_1,sel,
output wire [7:0] filter_out
);//sel,sel_1=11,1111,low pass,00,-133-1,high pass,01, 1331,band pass




//internal variables
wire signed [9:0] rg5,rg6,out2,out3,oua,oub;
wire signed [10:0] rg7;
wire signed [7:0] rg8,rg9;
wire sel_2;








// instructions
shifter1 M3(.out_shifter1(oua),.in_shifter1(rg2));
shifter1 M4(.out_shifter1(oub),.in_shifter1(rg3));


mux2 M0(.out_mux2(out2),.in1_mux2(rg2),.in2_mux2(oua),.sel_mux2(sel));
mux2 M1(.out_mux2(out3),.in1_mux2(rg3),.in2_mux2(oub),.sel_mux2(sel));


adder M7(.out_adder(rg5),.in1_adder(rg1),.in2_adder(out2),.sel_adder(sel_1));
adder M8(.out_adder(rg6),.in1_adder(rg4),.in2_adder(out3),.sel_adder(sel_1));






assign rg7=rg5+rg6;


shifter2 M5(.out_shifter2(rg8),.in_shifter2(rg7));
shifter3 M6(.out_shifter3(rg9),.in_shifter3(rg7));
if(sel==sel_1)
sel_2=1;
else if (sel=0&sel_1=1)
sel_2=0;
else filter_out=z;
muxout M2(.out_muxout(filter_out),.in1_muxout(rg8),.in2_muxout(rg9),.sel_muxout(sel_2));








endmodule
//submodule






//submodule_adder




module adder(out_adder,in1_adder,in2_adder,sel_adder);
input signed[7:0] in1_adder;
input signed[9:0] in2_adder;
input sel_adder;
output signed[9:0] out_adder;
wire signed [7:0] in1_adder_1;
if(sel_adder)
out_adder=in1_adder+in2_adder;
else
begin
in1_adder_1=~in1_adder+1;
out_adder=in1_adder_1+in2_adder;
end
endmodule
//rg1 add rg2,sel=1, rg=rg;sel=0,rg be minus. nothing to rg2.






module mux2(out_mux2,in1_mux2,in2_mux2,sel_mux2);
input [7:0]in1_mux2;
input [9:0]in2_mux2;
input sel_mux2;
output out_mux2;
if(sel_mux2)
out=in1_mux2;
else
out=in2_mux2;
endmodule
// sel=1 , rg=rg ; sel=0 , rg=3rg , nothing to shifter.




module muxout(out_muxout,in1_muxout,in2_muxout,sel_muxout);
input [7:0]in1_muxout;
input [7:0]in2_muxout;
input sel_muxout;
output out_muxout;
if(sel_muxout)
out_muxout=in2_muxout;
else
out_muxout=in1_muxout;
endmodule
//mux for output,sel=1,out=2,sel=0,out=1




module shifter1(out_shifter1,in_shifter1);//3倍
input [7:0]in_shifter1;
output [9:0]out_shifter1;
wire [8:0]out_shifter1_1;
assign out_shifter1_1={in_shifter1,0};
assign out_shifter1=out_shifter1_1+in_shifter1;
endmodule


// no sel, just rg = 3rg.


module shifter2(out_shifter2,in_shifter2);//除以4
input [9:0]in_shifter2;
output [7:0]out_shifter2;
assign out_shifter2=in_shifter2[9:2];
endmodule




module shifter3(out_shifter3,in_shifter3);//除以8
input [10:0]in_shifter3;
output [7:0]out_shifter3;
assign out_shifter3=in_shifter3[10:3];
endmodule






错误提示：
Error (10170): Verilog HDL syntax error at filter.v(37) near text "if"; expecting "endmodule"
Error (10112): Ignored design unit "filter" at filter.v(2) due to previous errors
Error (10170): Verilog HDL syntax error at filter.v(61) near text "if"; expecting "endmodule"
Error (10112): Ignored design unit "adder" at filter.v(55) due to previous errors
Error (10170): Verilog HDL syntax error at filter.v(78) near text "if"; expecting "endmodule"
Error (10112): Ignored design unit "mux2" at filter.v(73) due to previous errors
Error (10170): Verilog HDL syntax error at filter.v(91) near text "if"; expecting "endmodule"
Error (10112): Ignored design unit "muxout" at filter.v(86) due to previous errors
Error (10112): Ignored design unit "shifter1" at filter.v(99) due to previous errors
Error (10112): Ignored design unit "shifter2" at filter.v(109) due to previous errors
Error (10112): Ignored design unit "shifter3" at filter.v(116) due to previous errors

Zhangshuan

不能因为他们是自己给了我们喜欢这个问题一直困扰着

leopard520329

你的if,,,else.写的有点独特，放在always@（*）语句块试一下。不然就用条件语句assign a=b_en?c:d

gaurson

对，你这是C语言风格，不是HDL语法，哈哈。楼上说的对。

zleewin

谢谢 已解决