quartus中编译成功，但是modelsim中失败，大家能不能帮忙找找代码错在哪？

我的OK哦

modelsim报的错：** Error: (vlog-13069) D:/ModelSIM/test/mux4to1_stimulus.v(5): near "reg": syntax error, unexpected reg, expecting import or ';' or '#' or '('.

激励代码：
//激励模块
module stimulus;

//声明输入输出变量
reg IN0, IN1, IN2, IN3;
reg S1, S0;
wire OUT;

//调用4选1多路开关
mux4to1 mux41(OUT, IN0, IN1, IN2, IN3, S1, S0);

//设置激励信号
initial
begin
        IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
        #1 $display("IN0 = %b, IN1 = %b, IN2 = %b, IN3 = %b\n", IN0, IN1, IN2, IN3);

//选择IN0
        S1 = 0; S0 = 0;
        #1 $display("S1 = %b, S0 = %b, OUT = %b\n", S1, S0, OUT);

//选择IN1
        S1 = 0; S0 = 1;
        #1 $display("S1 = %b, S0 = %b, OUT = %b\n", S1, S0, OUT);

//选择IN2
        S1 = 1; S0 = 0;
        #1 $display("S1 = %b, S0 = %b, OUT = %b\n", S1, S0, OUT);

//选择IN3
        S1 = 1; S0 = 1;
        #1 $display("S1 = %b, S0 = %b, OUT = %b\n", S1, S0, OUT);
end

endmodule

4选1开关代码：
//门级定义4选1多路开关
module mux4to1(out, i0, i1, i2, i3, s1, s0);

//声明端口
output out;
input i0, i1, i2, i3;
input s1, s0;

//声明内部线网
wire s1n, s0n; //控制信号的逻辑反
wire y0, y1, y2, y3; //第一级与门的输出信号

//生成s1n和s0n信号
not (s1n, s1);
not (s0n, s0);

//调用三输入与门生成y信号
and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);

//调用或门输出被选择的信号
or (out, y0, y1, y2, y3);

endmodule

我的OK哦

初学verilog，希望大佬们帮帮忙，感谢！

我的OK哦

找到错误了，原来是我没保存，让各位见笑了