DDR3 V.S. DDR4 V.S. DDR5

固执的寻觅

[td]

Feature/Option	DDR3	DDR4	DDR4 Advantage
Voltage (core and I/O)	1.5V	1.2V	Reduces memory power demand
VREF inputs	2 – DQs and CMD/ADDR	1 – CMD/ADDR	VREFDQ now internal
Low voltage standard	Yes (DDR3L at 1.35V)	No	Memory power reductions
Data rate (Mb/s)	800, 1066, 1333, 1600, 1866, 2133	1600, 1866, 2133, 2400, 2666, 3200	Migration to higher‐speed I/O
Densities	512Mb–8Gb	2Gb–16Gb	Better enablement for large-capacity memory subsystems
Internal banks	8	16	More banks
Bank groups (BG)	0	4	Faster burst accesses
tCK – DLL enabled	300 MHz to 800 MHz	667 MHz to 1.6 GHz	Higher data rates
t CK – DLL disabled	10 MHz to 125 MHz (optional)	Undefined to 125 MHz	DLL-off now fully supported
Read latency	AL + CL	AL + CL	Expanded values
Write latency	AL + CWL	AL + CWL	Expanded values
DQ driver (ALT)	40Ω	48Ω	Optimized for PtP (point-to-point) applications
DQ bus	SSTL15	POD12	Mitigate I/O noise and power
RTT values (in Ω)	120, 60, 40, 30, 20	240, 120, 80, 60, 48, 40, 34	Support higher data rates
RTT not allowed	READ bursts	Disables during READ bursts	Ease-of-use
ODT modes	Nominal, dynamic	Nominal, dynamic, park	Additional control mode; supports OTF value change
ODT control	ODT signaling required	ODT signaling not required	Ease of ODT control, allows non-ODT routing on PtP applications
Multipurpose register (MPR)	Four registers – 1 defined, 3 RFU	Four registers – 3 defined, 1 RFU

固执的寻觅

[td]

Feature/Option	DDR4	DDR5	DDR5 Advantage
Data rates	1600-3200 MT/s	3200-6400 MT/s	Increases performance and bandwidth
VDD/VDDQ/VPP	1.2/1.2/2.5	1.1/1.1/1.8	Lowers power
Internal VREF	VREFDQ	VREFDQ, VREFCA, VREFCS	Improves voltage margins, reduces BOM costs
Device densities	2Gb-16Gb	8Gb-64Gb	Enables larger monolithic devices
Prefetch	8n	16n	Keeps the internal core clock low
DQ receiver equalization	CTLE	DFE	Improves opening of the received DQ data eyes inside the DRAM
Duty cycle adjustment (DCA)	None	DQS and DQ	Improves signaling on the transmitted DQ/DQS pins
Internal DQS delay monitoring	None	DQS interval oscillator	Increases robustness against environmental changes
On-die ECC	None	128b+8b SEC, error check and scrub	Strengthens on-chip RAS
CRC	Write	Read/Write	Strengthens system RAS by protecting read data
Bank groups (BG)/banks	4 BG x 4 banks (x4/x8) 2 BG x 4 banks (x16)	8 BG x 2 banks (8Gb x4/x8) 4 BG x 2 banks (8Gb x16) 8 BG x 4 banks (16-64Gb x4/x8) 4 BG x 4 banks (16-64Gb x16)	Improves bandwidth/performance
Command/address interface	ODT, CKE, ACT, RAS, CAS, WE, A<X:0>	CA<13:0>	[size=1.125] Dramatically reduces the CA pin count
ODT	DQ, DQS, DM/DBI	DQ, DQS, DM, CA bus	Improves signal integrity, reduces  BOM costs
Burst length	BL8 (and BL4)	BL16, BL32 (and BC8 OTF, BL32 OTF)	Allows 64B cache line fetch with only 1 DIMM subchannel.
MIR (“mirror” pin)	None	Yes	Improves DIMM signaling
Bus inversion	Data bus inversion (DBI)	Command/address inversion (CAI)	Reduces VDDQ noise on modules
CA training, CS training	None	CA training, CS training	Improves timing margin on CA and CS pins
Write leveling training modes	Yes	Improved	Compensates for unmatched DQ-DQS path
Read training patterns	Possible with the MPR	Dedicated MRs for serial (userdefined), clock and LFSR -generated training patterns	Makes read timing margin more robust
Mode registers	7 x 17 bits	Up to 256 x 8 bits (LPDDR type read/write)	Provides room to expand
PRECHARGE commands	All bank and per bank	All bank, per bank, and same bank	PREsb enables precharging-specific bank in each BG
REFRESH commands	All bank	All bank and same bank	REFsb enables refreshing of specific bank in each BG
Loopback mode	None	Yes	Enables testing of the DQ and DQS signaling

lwjee

楼主有没有进一步详细的资料？

固执的寻觅

lwjee 发表于 2020-5-22 15:10
楼主有没有进一步详细的资料？

好久不见 你头像很清纯啊~

这个是不是只能看标准了

lwjee

固执的寻觅 发表于 2020-5-22 17:02
好久不见 你头像很清纯啊~

这个是不是只能看标准了

谢谢！

longheshang

aoli

不错！

xd_laoxie

感谢！

mismatch24

固执的寻觅 发表于 2020-3-11 10:35
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有个错误，write leveling不是补偿tDQS2DQ的，write training才是

轩辕志瑜

谢谢楼主分享