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各位大神,
小弟刚开始学习chipscope软件,不知道为什么设置的触发信号会在不满足的时候仍然能够抓到信号。望赐教
工程代码很简单,一个led灯代码
module led_test
(
input clk, // system clock 50Mhz on board
input rst_n, // reset ,low active
input key1,
output reg[3:0] led // LED,use for control the LED signal on board
);
localparam LED_TICK_TIME = 1000;//1000ms
localparam CLK_HZ = 50000000;
//localparam LED_TICK_COUNTER = CLK_HZ*1000/LED_TICK_TIME;
localparam LED_TICK_COUNTER = CLK_HZ/LED_TICK_TIME*1000;
//define the time counter
reg [31:0] timer;
// 计时器
always@(posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
timer <= 32'd0; //when the reset signal valid,time counter clearing
else if (timer == (LED_TICK_COUNTER*4-1)) //4 seconds count(50M*4-1=199999999)
timer <= 32'd0; //count done,clearing the time counter
else
timer <= timer + 32'd1; //timer counter = timer counter + 1
end
//LED计时控制
always@(posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0) //reset signal active
led <= 4'b0000;
else if (timer == (LED_TICK_COUNTER-1)) //time counter count to 1st sec,LED1 lighten
led <= 4'b0001;
else if (timer == (LED_TICK_COUNTER*2-1)) //time counter count to 2nd sec,LED2 lighten
led <= 4'b0010;
else if (timer == (LED_TICK_COUNTER*3-1)) //time counter count to 3rd sec,LED3 lighten
led <= 4'b0100;
else if (timer == (LED_TICK_COUNTER*4-1)) //time counter count to 4th sec,LED4 lighten
led <= 4'b1000;
end
抓取时钟使用的是clk_BUFGP
触发信号使用的是rst_n_IBUF
触发条件是下降沿(上升沿和高低电平也都测试过)
无论如何设置,总是能抓取到信号
按照我的理解:应该是在我设置了rst_n_IBUF信号下降沿触发以后,必须是我按下板子的按钮产生rst_n有效时才能触发抓取信号,但是为何随时都能抓取呢
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