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如下执行指令,编译过程中指示NULL不认识,编译器使用的是vcs2014版本。因为没权限修改SVP的代码,有什么办法让编译通过?
./run_usb_svt_uvm_basic_sys basic_additional_20_enumeration vcsvlog -w
Copying top.usb_20_serial.sv as top_test.sv
# rm -rf output logs coverage
# mkdir output logs coverage
# vcs -l ./logs/compile.log -q -Mdir=./output/csrc -ntb_opts uvm -full64 -sverilog +define+UVM_DISABLE_AUTO_ITEM_RECORDING +define+UVM_PACKER_MAX_BYTES=24000 -unit_timescale=1ps/1ps +warn=noFCDCI +define+SVT_UVM_TECHNOLOGY +define+SYNOPSYS_SV +incdir+/proj/soc707/wa/zqmao/usb_svt/src/sverilog/vcs +incdir+/proj/soc707/wa/zqmao/usb_svt/include/sverilog +incdir+/proj/soc707/wa/zqmao/usb_svt/src/verilog/vcs +incdir+/proj/soc707/wa/zqmao/usb_svt/include/verilog +incdir+/proj/soc707/wa/zqmao/usb_svt/examples/sverilog/usb_svt/tb_usb_svt_uvm_basic_sys/{.,../../env,../env,env,dut,hdl_interconnect,lib,tests} -o ./output/simvcssvlog -f top_files -f hdl_files
Error-[ICVT] Illegal constraint variable type
/eda/synopsys/synopsys_VIP/vip/vip/svt/usb_svt/M-2017.06/sverilog/src/vcs/svt_usb_20_na_30_ss_transfer_system_virtual_sequence_collection.svp, 8807
svt_usb_uvm_pkg, "ep_cfg"
The identifier 'ep_cfg' must be an integral type, an enum type, or of type
'bit'.
Change the type of the random variable 'ep_cfg' to an integral, bit, or enum
type.
Error-[NYI-NIC] Null in constraints not yet implemented
/eda/synopsys/synopsys_VIP/vip/vip/svt/usb_svt/M-2017.06/sverilog/src/vcs/svt_usb_20_na_30_ss_transfer_system_virtual_sequence_collection.svp, 8807
svt_usb_uvm_pkg, "null"
'null' was used in a constraint expression. This is not yet supported.
Remove 'null' from the constraint expression.
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