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[招聘] 内推:ARM中国深圳上海招聘AIIP验证工程师

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发表于 2019-12-18 17:33:53 | 显示全部楼层 |阅读模式

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邮箱:lunping.guo@armchina.com


Design Verification Engineer for AI
社招PD AI全职R&D
广东·深圳市上海市·闵行区


职位描述

As a Design Verification Engineer, you will contribute to RTL verification for Artificial Intelligence (AI) related IP work on cutting-edge AI technique from idea to implementation.
Your responsibilities will be related, but not limited to:
·      Work with design team and drive IP design into verification convergence
·      Create module verification plan, keep track of the verification status
·      Build up testbench and write normal/corner test cases to cover design function
·      Debug failure cases and has insight understanding of the design
·      Work closely with software team in hardware-software codesign flow
Skills and Experience:
·      Degree from EE. CS and good plus with qualifications from circuit design
·      2 to 5 years design verification experience
·      Good understanding of CPU or DSP architecture, memory/bus architecture and assembly language for ARM or other architecture
·      Deep understanding of design verification methodology
·      Thorough knowledge of System Verilog and UVM, C or C++
·      Hands on experience on functional verification environment implementation, test case writing and RTL functional debug
·      Experience in specification, creation, and debug of System Verilog/UVM constrained-random testbench
·      Familiar with scripting language such as Perl, TCL, Python
·      With excellent communication skill, teamwork and attention to details





 楼主| 发表于 2019-12-24 09:29:29 | 显示全部楼层
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 楼主| 发表于 2019-12-24 09:33:56 | 显示全部楼层
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