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发表于 2019-12-13 17:09:01
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DRC Rule C1
Message Text
Clock Rule C1: Clock PIs off failed to force off clock input N of scan S I (G).
Severity
Error
Examples
Example 1: Scan chain with a master-slave configuration
Example 2, below, displays an integrated cell using a latch-based gating style, rising-edge-triggered. The integrated cell contains test logic scan enable.
Example 2: Rising-Edge Latch-Based Integrated Cell With Post-Control (latch_posedge_postcontrol)
Example 3, below, displays an integrated cell using a latch-based gating style, falling-edge-triggered. The integrated cell contains test logic scan enable.
Example 3: Falling-Edge Latch-Based Integrated Cell With Post-Control (latch_negedge_postcontrol)
Description
When all clocks ports are at their off state, all clock/set/reset inputs of scan state elements must be at their off state. The only exception to this would be if these inputs were causing a capture of data from within the scan cell in which they reside such as when a slave latch captures data from its master latch.
N is the input port number of the ATPG primitive (set=0, rst=1, clk1=2, data1=3...), S is the name of the scan chain, I is the instance pathname, and G is the gate ID number of the device.
Failure to satisfy this rule can result in scan cells failing to hold their value before capture, and there is a high risk that patterns generated would fail in simulation. Scan based simulation continues to assume that the values captured during a capture clock cycle are the result of state element values that existed at the end of the load operation. This assumption might be false if scan cells fail to hold their value and lead to patterns generated that fail simulation.
This check is performed by simulating the logic values that result when:
clocks are at their off state
constrained ports are set to their constrained values
constant value nonscan cells are set to their constant state
nonscan cells which have constant values are determined automatically during circuit learning.
This rule violation occurs if any clock/set/reset input of any scan cell memory element is not at its off state.
What Next
A common cause of this violation is a missing clock definition or a clock defined with the wrong polarity.
Another common cause is a clock which passes through a MUX, and the select line of the MUX is not constant. If the MUX is controlled by some sort of test mode port, that port should be constrained with an add_pi_constraint command.
A violation can be analyzed using the schematic viewer by selecting its violation ID number from the ANALYZE button. This changes the pin data reporting to clock-off data and displays the failing cell with all the gates in the backtrace cone of the failing input. This shows the failing clock/set/reset input and tracing back from this input can assist you in determining how to correct the problem. |
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