有小哥哥吗？清华大学李福乐的SAR ADC 的SAR逻辑控制知识点

月落小青青

准备做一个SAR ADC ,看到群里发的李福乐老师的ppt讲义，有一个点一直看不懂。
1：这个下方触发器的时钟是什么意思？左下方第一个触发器的时钟从哪来的，理论上不是按照D7、D6、d5依次顺序出来的吗？如果D6没出来，D7的时钟从哪来？
2：这个逻辑功能怎么实现，无法理解。。
有大佬小哥哥给解答一下吗？？？？？

yuechuan

1. Estimate D7 = 1 by asserting DFF set pin.
2. Compare the dac output with input, comparator output ready  
3. Estimate D6 = 1 in the next clock cycle by asserting DFF set pin --> D6 goes high, This is the clock for D7. The comparator output is latched into D7 at this moment.

月落小青青

yuechuan 发表于 2019-7-26 22:00
1. Estimate D7 = 1 by asserting DFF set pin.
2. Compare the dac output with input, comparator outpu ...

thank  you very  much  

月落小青青

yuechuan 发表于 2019-7-26 22:00
1. Estimate D7 = 1 by asserting DFF set pin.
2. Compare the dac output with input, comparator outpu ...

大佬，再问你一个问题？
1：根据电容上下对称的话，他应该只画了一半吧。图中有2x9个寄存器，我应该还加上9个吗

yuechuan

No, you only need one SAR logic (2x9 DFFs) as a global timing signal. If you are designing a differential SAR ADC, you need two sets of complementary switching logic circuits that control the differential CDAC.  But they can share the same SAR logic.

月落小青青

i  coundnt undersrtand  it. how can i share  ,can  you give me some  tips

月落小青青

yuechuan 发表于 2019-7-27 10:23
No, you only need one SAR logic (2x9 DFFs) as a global timing signal. If you are designing a differe ..

yes ,i  design a differential  adc
i  coundnt undersrtand  it. how can i share  ,can  you give me some  tips  ?i guess  if d7 is a port from a DFFS,and  another  d7_n is  also from this  DFFS,  becasuse  DFFS   have    a    q  and  q_    outports ,  its a  right  idea?

thank  little   bros    very  much ！！！！

yuechuan

Differential SAR ADC ususally means the CDAC is differential. Your output is just a digital code representing the differential input signal. So the output only need one register (9x DFFs on the bottom) to store the result. And your SAR logic is basically just estimating the nth bit is 1 and then shift to the next, which also does not require another set of DFFs. Your differential CDAC switches will need complementary logic (for example if one of the top CDAC switch is off then the corresponding bottom switch is probably on). So you need TWO sets of switch driving logic.

月落小青青

yuechuan 发表于 2019-7-29 10:30
Differential SAR ADC ususally means the CDAC is differential. Your output is just a digital code rep ...

This    is   to say   I    totally   need  9X3  DFF   if  i   drive   differential  cap ,   9 DFFS   for  SAR LOGGIC,which  is shared  ,  9*2 DFFS for   driving   logic    , when   one set  is off   ,another set is  on

yuechuan

You can make it work this way.