For timing_corner test_corner_max:setup, late:
Slew time target (leaf): 0.276ns
Slew time target (trunk): 0.276ns
Slew time target (top): 0.277ns
Buffer unit delay for power_domain PDcore and effective power_domain PDcore: 0.155ns
Buffer max distance for power_domain PDcore and effective power_domain PDcore: 1565.977um
Fastest wire driving cells and distances for power_domain PDcore and effective power_domain PDcore:
Buffer : {lib_cell:CLKBUFX32M, fastest_considered_half_corner=tsc1906_corner_max:setup.late, maxDistance=1565.977um, maxSlew=0.241ns, speed=5223.405um per ns, cellArea=15.028um^2 per 1000um}
Inverter : {lib_cell:CLKINVX40M, fastest_considered_half_corner=tsc1906_corner_max:setup.late, maxDistance=1468.205um, maxSlew=0.244ns, speed=6983.139um per ns, cellArea=16.831um^2 per 1000um}
Clock gate: {lib_cell:TLATNTSCAX20M, fastest_considered_half_corner=tsc1906_corner_max:setup.late, maxDistance=313.089um, maxSlew=0.253ns, speed=1203.726um per ns, cellArea=229.260um^2 per 1000um}
Clock tree balancer configuration for clock_tree vco_clk_generator_for_vco_clk<2>:
Non-default CCOpt properties for clock tree vco_clk_generator_for_vco_clk<2>:
route_type (leaf): default_route_type_leaf (default: default)
route_type (trunk): default_route_type_nonleaf (default: default)
route_type (top): default_route_type_nonleaf (default: default)
**ERROR: (IMPCCOPT-1146): Clock tree vco_clk_generator_for_vco_clk<2> cannot use the following cells.
CTS will not be able to run on this clock tree.
FRAME_ROM16KX8 is cant_use for the following reasons: property capacitance_override not fully specified. This affects the following instances: i_TEST/i_MCU/i_Memory/X2678/CK
The CCOpt property capacitance_override is set, but not for input all pins, delay corners, or events.
Validating CTS configuration done.
**ERROR: (IMPCCOPT-2196): Cannot run ccopt_design because the command prerequisites were not met. Review the previous error messages for more details about the failure.