在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 750|回复: 3

[招聘] Cadence 7月份最新内推职位 急徵 上海/北京/深圳

[复制链接]
发表于 2019-7-11 02:34:45 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
符合條件的可嘗試,内推成功率大

有问题可加微信询问leviathanist
简历请投递至 3114835608@qq.com
Thanks.

A.
Position: Lead Product Engineer
Location: SH/BJ/SZ

Job Description
VIP PE is expected to be an expert in a specific domain of Verification IP family protocol and product wise.
VIP PE main role is to be Sales acceleration for top Cadence accounts and enable pre-sales technical activities and product adoptions.
To ensure that, one must be verification expert and understand customer design and verification flow.
As VIP Product Engineer we must be able to be translating high level requirement that coming from customers to technical spec and define a solution that fits to customer needs.
Engineer is expected to work both independently and in collaboration with other team members (RnD, Marketing, support) to ensure all dimension of the product are aligned.
This role requires some travels to customer sites.

Requirements
Experience with Developing Verification environments using System Verilog.
Familiar with the UVM methodology Familiar with standard protocol like USB/ PCIE/Mipi/AMBA Experience with Unix / Linux environment.
Very good English, capable to have fluent discussions and communicate Face to Face and through emails.
Team orientation, mature work attitude and good judgment under pressure Customer service approach.

B.
Job Title: Associate / Compliance Analyst (软件合规专员)
Location: Shanghai

Position Description:
Providing support and driving License Compliance case in Asia as part of Software Operations and license Compliance at Cadence (SOLC).
Software Operations and License Compliance is a technical and business value add function at Cadence. Responsible for delivering innovative solutions for Licensing, Software Delivery, Installation and Compliance; SOLC is not only a tech powerhouse, but a revenue generating function.
Cadence employs a Compliance Analyst Assistant to support license compliance program and operations in Asia, especially in China.
Position requires good analytical, communication and collaboration skills.  Providing support for on-going compliance cases, including infringement data system tracking, case preparation, regular status reports, partnering with distributors and legal firms in China.
Position Requirements:
Essential Job Functions
Compliance case operations; generate case reports, analyze, co-work with channel partners to initiate actions, collect status report regularly
Compliance systems management, track infringement data trend, track and report on infringing organizations.
Compliance case report: gather case updates and collate reports monthly, close-won settlement recording in Dashboard.
Document all actions; Compliance case summary preparation, Legal Work Request for settlement agreement drafting, payment processing to outside law firms.
Other daily operational support
Knowledge, Education, Skills, Abilities, and Experience Required
Bachelor’s Degree required.
Sales and / Or Operational background in software industry
Experience in Compliance / Audit would be desirable
3-8 Years’ work experience, able to work with team(s)
Experience working with systems / applications, like salesforce would be desirable
Ability to communicate clearly in English, both verbally and in writing is must.

C.
Title: Front-end Design Engineer (RTL Coding)  数字前端设计
Location: SH/BJ

Position Description:
Deliver/implement DDR IP. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.

Specific duties include:
- Be responsible for building and leading a high-performance IC design team, owning the IC micro-architecture, package and test platform development, refining the EDA design flow
- Proficiency in logic design, simulation, synthesis, STA and testing
- Proficiency in Verilog and its simulation environment
- Good knowledge of IC design

Position Requirements:
1. Essential Qualifications: Must have BS degree with 4+ years of applicable experience, MS degree with 2+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
2. Essential that the individual demonstrates strong communication, verbal and written.
3. Requires good communication skills in English.



 楼主| 发表于 2019-7-11 19:07:55 | 显示全部楼层
add vacancy

D.
Principal/Lead Application Engineer (Front-end Verification)
Location: Beijing/Shanghai/Shenzhen

Position Description:
1.Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, simulation Emulation and Acceleration products.
2.Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
3.Train, ramp-up and accompany customer project.
4.Conduct basic and advanced trainings, presentations and demos as necessary.
5.Providing technical expertise to address clients’ queries, which need expert involvement.
6.Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.

Position Requirements:  4-6 or above years’ experience in the following areas:
Design experience in Verilog/VHDL for IP or SoC chip level.
HW verification with knowledge of System Verilog/VHDL and HDL simulators
FPGA prototyping project experience
Experience with hardware emulator or accelerator is a big advantage
Advanced Verification Methodology like UVM is a plus
Knowledge of Unix and Linux is highly desired
Strong verbal and written communication skills in English
Strong teamwork skills with good human relationship


 楼主| 发表于 2019-7-12 21:12:40 | 显示全部楼层
add vacacies

E.
Title: Lead / Principle Front-end Design Engineer (RTL Coding)  数字前端设计
Location: SH/BJ

Position Description:
Deliver/implement DDR IP. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.

Specific duties include:
- Be responsible for building and leading a high-performance IC design team, owning the IC micro-architecture, package and test platform development, refining the EDA design flow
- Proficiency in logic design, simulation, synthesis, STA and testing
- Proficiency in Verilog and its simulation environment
- Good knowledge of IC design

Position Requirements:
1. Essential Qualifications: Must have BS degree with 4+ years of applicable experience, MS degree with 2+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
2. Essential that the individual demonstrates strong communication, verbal and written.
3. Requires good communication skills in English.



F.
Title: Lead Design Engineer (Synthesis)  数字前端实现
Location: SH

Position Description:
- In charge of DDR IP logic design Implementation
- Daily duties include: RTL coding(plus), Logic Synthesis(must), Static Timing Analysis(must)
- HDL language Knowledge, like verilog or vhdl is necessary
- C/C++/perl/tcl/csh/python, UNIX, Linux experience are plus
- Excellent analytical and problem-solving skills. Quick learner-able to learn and apply technical and complex topics
- Excellent communication skills and the uncanny ability in a cooperative team environment are required
- Self-motivated, result-oriented, can take ownership and follow-through on tasks

Position Requirements:
1. Master degree with 4~7 years’ experience
2. Major in Micro-electronics, Electronic Engineering, Computer Science, Information Technology or equivalent
3. Ability to work effectively alone or as well as in the team
4. Essential that the individual demonstrates strong communication, verbal and written
5. Requires good communication skills in English
6. Experience of DDR is preferred




 楼主| 发表于 2019-7-16 20:03:26 | 显示全部楼层
G.
Lead Product Validation Engineer (SI/PI) -工作地点:上海
Position: Lead Product Validation Engineer

Job Description
Sigrity Shanghai Product Validation team is looking for an engineer with experience in signal integrity/power integrity analysis and product verification. You will be responsible for testing and overseeing the quality management of Sigrity products, the industry leading SI/PI analysis products. You will be involved in world latest SI/PI analysis technologies development to help our customers create most innovative products.

Duties:
Work within a global multi-functional team to review SI/PI analysis technologies, project plans and functional specifications, develop test criteria and write test plans, manually exercise and test functionality of the Sigrity products
Develop automated tests within the existing test environment
Maintain comprehensive regression suites for monitoring products quality
Work with the team to solve customer issues

Requirements:
BS degree or MS degree with 2+ years SI/PI related experience
Understand test processes and methodologies in a software development environment
Good understanding of power integrity and signal integrity
Be familiar with Linux system, and scripting skills with TCL or Perl or Shell is a plus
Knowledge of PCB design, routing, and packaging is a plus
Having good analytical and problem solving skills is essential
Strong written and verbal communication skills, in English and Chinese are mandatory
Self-starter, self-sufficient, able to work independently as well as with teams, able to multitask


您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /2 下一条


小黑屋| 手机版| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-11-26 04:21 , Processed in 0.019253 second(s), 10 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表