在Modelsim用自带的uvm库,想编译一下,搞了两天了,还是编译失败,求助大神解答一下啊!!!十分感谢,下边是我的操作过程
vlib work
set UVM_HOME D:/modelsim/verilog_src/uvm-1.1a
# D:/modelsim/verilog_src/uvm-1.1a
set WORK_HOME D:/UVM_PROJECT
# D:/UVM_PROJECT
vlog +incdir+$UVM_HOME/src -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF $UVM_HOME/src/uvm_pkg.sv $WORK_HOME/helloworld.sv
# Model Technology ModelSim SE vlog 10.1a Compiler 2012.02 Feb 22 2012
# -- Compiling package uvm_pkg (uvm-1.1a Built-in)
# ** Warning: D:/modelsim/verilog_src/uvm-1.1a/src/uvm_pkg.sv(29): (vlog-2275) 'uvm_pkg' already exists and will be overwritten.
#
# -- Compiling package uvm_pkg (uvm-1.1a Built-in)
# -- Compiling module hello_world_example
# ** Error: D:/UVM_PROJECT/helloworld.sv(3): Could not find the package (umv_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.
# D:/modelsim/win32/vlog failed.
这是我的helloworld.sv文件
`include "uvm_pkg.sv"
module hello_world_example;
import umv_pkg::*;
`include "uvm_macros.svh"
initial begin
`uvm_info("info1","Hello UVM!",UVM_LOW)
end
endmodule: hello_world_example