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用vcs做后仿出现以下错误:Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03; Runtime version I-2014.03; Jun 4 15:56 2019
VCD+ Writer I-2014.03 Copyright (c) 1991-2014 by Synopsys Inc.
The file '/home/IC/Desktop/EDA/post_sim/vcs_post_sim/inter.vpd' was opened successfully.
20000000 ps
"smic18.v", 8751: Timing violation in calendar_tb.U.\week_reg[2]
$hold( posedge SN:1000, posedge RN:1000, limit: 1000 );
"smic18.v", 9621: Timing violation in calendar_tb.U.min_carry_reg
$setuphold( posedge CK &&& (flag == 1'b1):5000, posedge E:5000, limits: (1000,500) );
"smic18.v", 7679: Timing violation in calendar_tb.U.day_carry_reg
$setuphold( posedge CK:1004000, posedge RN:1004000, limits: (1000,500) );
"smic18.v", 8751: Timing violation in calendar_tb.U.\year_reg[3]
$hold( posedge SN:8013000, posedge RN:8013000, limit: 1000 );
"smic18.v", 8751: Timing violation in calendar_tb.U.\year_reg[0]
$hold( posedge SN:8013000, posedge RN:8013000, limit: 1000 );
这些违反怎么理解啊?还有怎么修改啊?新人求教!!!先谢谢了
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