北京上海成都数字后端全定制职位招聘

daisyyang

北京、上海、成都数字后端职位招聘，有兴趣欢迎联系我了解详情，微信 yy17cc，邮箱daisy@hibohr.com



ASIC后端 Design Engineer
Job description:
1. Perform floor-planning, physical synthesis, clock tree and clock gating design, power gating, routing, layout, integration and physical verification
2. Solve deep sub-micron design problems such as leakage, power, signal integrity, DFM, DFT etc.
3. Independently assess and drive complex digital physical design projects
4. Enhance IC physical design flow methodology
5.Perform power, performance and area benchmark for new technology adoption
6.Develop Perl/TCL/Shell scripts for flow and procedure automation
7. Work proactively with EDA engineers and tool suppliers to debug tool functionality and bugs
8. Support failure analysis
Qualifications:
1.BS or above in Electrical Engineering with 4-year experience,
2. Complete knowledge of full design IC implementation and signoff process
3. Experienced with using Cadence Encounter, Synopsys ICC, ETS, Prime Time, PVS, QRC, Calibre, XRC, Hercules, StarRC etc.
4. Proficient in STA, power analysis, DRC/LVS/PEX/DFM, noise, static and dynamic IR drop analysis
5. Expertise in low power flow (power gating, multi-Vt, voltage islands, adaptive or dynamic voltage scaling etc)
6. Good UNIX background and Perl/Shell/SKILL scripting skills
7. Good written and verbal communication capability and proficient in both English and Mandarin
8.Strong time management and multi-tasking skills that enable on-time delivery
Analytical and persistent in resolving technical issues





全定制芯片工程师
职位概述
1、在最先进技术节点进行各种类型的晶体管级电路设计，如静态/动态逻辑, 时钟相关电路等；
2、极具挑战的超低电压高能效电路设计和优化。
任职条件
1、对逻辑门/运算放大器/BGR等的相关基础概念有深刻的理解；
2、对低电压低功耗CMOS电路设计有较好的理解。
掌握工具：
1、熟练使用EDA工具，如HSPICE, Cadence Virtuoso schematic/layout 编辑器；
2、熟练使用Python, Perl, TCL，Skill等至少一种脚本语言。
岗位职责
High performance, low power, small area custom digital circuit design for processors·
Circuit architecting, simulation and characterization of custom design circuit.
1. Transistor level function verification.
2. Participating in building CAD flow for circuit design.
3. Layout floor planning and supervision.
任职条件
1. BSEE minimum, MSEE preferredwith 1-5 years of working experience;
2. Strong background in deep submicron CMOS process and device.
3. Good knowledge in high speed digitalcircuit design techniques.
4. Experience in circuit simulation, schematic capture and layout verification CAD tools.
5. Must be a team player with effective written and verbal communication skills.
6. Quick learner and work independently.