Error (10228): Verilog HDL error at tb_modules.sv(1): module "mod_a" cannot be declared more than once File

我要学设计

各位大佬，Verilog初学者在HDLbits做题时遇到一个问题，mod_a没有被多次声明啊，为什么一直出现这个错误呢？代码如下：
module top_module ( input a, input b, output out );
    mod_a instance2 ( .out(out), .in1(a), .in2(b) );
endmodule
module mod_a ( input in1, input in2, output out );
    assign out=in1&in2;
endmodule


错误如下：
    Error (10228): Verilog HDL error at tb_modules.sv(1): module "mod_a" cannot be declared more than once File: /var/www/verilog/work/vlghG3SJN_dir/tb_modules.sv Line: 1Info (10499): HDL info at top_module.v(4): see declaration for object "mod_a" File: /var/www/verilog/work/vlghG3SJN_dir/top_module.v Line: 4Info (12021): Found 0 design units, including 0 entities, in source file tb_modules.svError: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning    Error: Peak virtual memory: 1036 megabytes    Error: Processing ended: Wed May 22 23:04:58 2019    Error: Elapsed time: 00:00:00    Error: Total CPU time (on all processors): 00:00:01Error (23031): Evaluation of Tcl script /var/www/verilog/template/compile.tcl unsuccessfulError: Quartus Prime Shell was unsuccessful. 7 errors, 1 warning    Error: Peak virtual memory: 902 megabytes    Error: Processing ended: Wed May 22 23:04:59 2019    Error: Elapsed time: 00:00:03    Error: Total CPU time (on all processors): 00:00:02

gaurson

你这些代码放在一个.v里面的？分成两个试试看，然后放到一个filelist里面。

我要学设计

大佬大佬，这是这道题的网址https://hdlbits.01xz.net/wiki/Module，他只留了一个空让写代码module top_module ( input a, input b, output out );
endmodule

snq31418

后面三行去掉，不需要定义mod_a

IC.Michael

我要学设计 发表于 2019-5-25 15:10
大佬大佬，这是这道题的网址https://hdlbits.01xz.net/wiki/Module，他只留了一个空让写代码module top_mod ...

这个网站好神奇！