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发表于 2019-5-22 11:50:18
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Before you learn UVM(or OVM/VMM), you should study SystemVerilog first,for UVM is a kind of verification method based on SV.
SystemVerilog for Verification--A Guide to Learning the Testbench Language Features(2nd Edition), by Chris Spear is a very popular book for IC designer&verify engineer.
If you are going to use UVM, you need download the 'uvm-1.1d'(or maybe it has been updated to latest version) releases package from: https://www.accellera.org/downloads/standards/uvm
The release includes source code in 'src' fold, and documents in 'doc'. The 'doc' will be very useful to you!
Hope this helps |
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