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楼主: trantung

[求助] Verification document

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 楼主| 发表于 2019-5-21 21:32:50 | 显示全部楼层
thank you
发表于 2019-5-22 11:50:18 | 显示全部楼层
   Before you learn UVM(or OVM/VMM), you should study SystemVerilog first,for UVM is a kind of verification method based on SV.
   SystemVerilog for Verification--A Guide to Learning the Testbench Language Features(2nd Edition),  by Chris Spear is a very popular book for IC designer&verify engineer.
   If you are going to use UVM, you need download the 'uvm-1.1d'(or maybe it has been updated to latest version) releases package from: https://www.accellera.org/downloads/standards/uvm
   The release includes source code in 'src' fold, and documents in 'doc'. The 'doc' will be very useful to you!
   Hope this helps
发表于 2019-5-22 11:53:23 | 显示全部楼层
hope this helps
发表于 2019-5-22 12:19:02 | 显示全部楼层
SystemVerilog验证 测试平台编写指南2
UVM实战卷1
发表于 2023-4-6 03:56:31 来自手机 | 显示全部楼层
Thanks
发表于 2023-4-6 20:16:41 | 显示全部楼层
waiguoren?
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