在线咨询 切换到宽版
eetop公众号 创芯大讲堂 创芯人才网

 找回密码
 注册

手机号码,快捷登录

手机号码,快捷登录

搜全文
查看: 865|回复: 0

[招聘] 数字设计工程师

[复制链接]
发表于 2019-5-17 13:29:15 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

×
NO.499-【猎头职位:上海需要一位   数字设计工程师】联系人:Raymond-Chen,邮箱:hr@kthr.com,微信也可查询职位了!打开手机微信,搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加,欢迎大家关注!
Job Description:
1.     Thisposition is for a digital/ASIC design engineer to build next-generationanalog/digital mixed SoC chips.
2.     Handlingevery aspect in ASIC design flow including architecture, RTL coding,Verification, Synthesis, DFT, STA and P&R.
3.        Participateinto the chip debug and validation.
Job Requirement:
1.     BSEEwith minimum 3-year of working experience or MSEE with minimum 1-year ofworking experience for starting position
2.     MSEEwith minimum 3-year of working experience for senior position.
3.     Excellentknowledge for ASIC design, such as MOS transistor, arithmetic structure(addition, multiplication), timing analysis, design for test, meta-stabilityand etc.
4.     Needfundamental understanding for digital signal processing, such as FIR/IIR filterstructure, digital error correction, decimation/interpolation and etc.
5.     Usageexperience (not all of them required) of industry-standard EDA tools, such asVCS/NC, Design Compiler, Primetime, Formality/Conformal and Tetramer/DFTcompiler.
6.     Experiencein bus design (SPI, I2C, AHB or AIX), data path design (Filter, correlation orCodec), SerDescontroller (PCS and MAC) and PHY (channel encoder/decoder) willbe a plus.
7.     Experiencein metrics driven verification methodology (system Verilog/UVM based) will be aplus.
8.        Experiencein every aspect of ASIC design will be a great plus.
福利:五险一金  年终奖金 KT二维码最小版.jpg

您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

手机版| 小黑屋| 关于我们| 联系我们| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2025-9-16 05:11 , Processed in 0.012153 second(s), 5 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表