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岗位1:数字设计工程师Write micro-architecture definition and design implementation Spec; Write RTL coding for block or top level; Do IP level synthesis/timing analysis/formality check/CDC check/Code coverage check; Assist verification engineers to complete module and top level simulation and verification; Debug RTL/Gate Level waveform at module or top level; 岗位2:FPGA工程师
BSEE/MSEE with 1+ years of expierence in FPGA prototyping; Expert in Xilinx Vivado FPGA design flow (block design and non-project flow) ; Expert in board level debugging; Expert in lab equipment, such as oscilloscope, etc; Expert in scripting (python/ tcl) ; Solid project experience in high speed timing closure (logic > 250MHz, IO > 500MHz); Deep knowledge in PCIe is a big plus; Knowledge in modern operation system is a plus;
岗位3:SI信号完整性
MS in Electrical Engineering/Microwave/Physics/Computer Science/Math; Knowledge of Electromagnetic and Microwave concepts; Knowledge of a programming or scripting language in a Windows/UNIX environment; Strong analytical and problem-solving skills; Passion for technology; Eager, quick learner with strong team-work spirit; Excellent technical communication skills.
岗位4:系统验证工程师(UVM)
Excellent team work style; Solid IP/SoC verification background; Mass production for verified IP/SoC; Bachelor with minimum 2 years of working experience in ASIC digital verification; Production experience in verification strategies and test plans; Familiar with System Verilog/UVM for test bench creation, debug, reuse, constrained-random stimulus and functional coverage; Production experience in ARM buses, such as AXI/AMBA/APB; Familiar with verification tools; Familiar with Linux, csh/Python or other script languages; Good English reading and writing skills.
工作地点:上海漕河泾,离地铁站不到3分钟路程 公司待遇行业领先,基本不加班 内推职位,非猎头,
有考虑的发简历到我邮箱610448613@qq.com,也可QQ私聊。
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