-v:specify a verilog library file。VCS looks in this file for definitions of the module and UDP instances that VCS found in you source code, but for which it didn't find the corresponding module or UDP definitions in you source code
我理解的是会在-v中寻找子模块的定义,但是不会寻找top的定义,但是直接使用vcs top submodule和vcs top -v submodule好像效果也是一样的?