vivado synthesis 报错

pp是pp

always @(posedge read_sig)
    begin @(posedge cpu_clock)
        reset_on_read <= 1'b1;
        @(posedge cpu_clock)
        reset_on_read <= 1'b0;
    end




[Synth 8-27] event control except as first statement of always block not supported ["C:/Users/asus/Desktop/AX7020_2017/ScsiTarget/cy_psoc3_dp.v":879]

phoenixson

建议回去学一下基本语法，你这个连入门级问题都算不上

robberxiong

你这写的不知道是啥？
跟软件关系应该不大