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岗位:FPGA工程师
职位描述:
Generate sub-module design specification from prototype architecture;
Design high-speed (>500MHz) circuit, including RTL coding, IP using, simulation, timing closure and bit file generation;
Port ASIC to FPGA, generate/run/debug test cases on FPGA;
Write design report;
Build up and maintain FPGA test platforms, including PCB schematic design and layout support.
职位要求:
BSEE with 3 years of experience in circuit design with FPGA;
More experience in IP using/debugging, such as PLL, MCU, PCIe and DDR4 interface;
Knowledge in DDR4 memory system and Intel server platform;
Familiar with lab equipment, such as oscilloscope and logic analyzer;
Familiar with PLD/FPGA design flow using Verilog and EDA tools such as Xilinx ISE and Altera Quartus;
Knowledge in TPM, encryption IP etc. is a plus.
工作地点:上海和昆山
非猎头,内部推荐,有考虑的发简历到我邮箱610448613@qq.com,也可QQ私聊。
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