Micron 急招 Senior IC Design Verification Engineer

Bellatan

[size=13.3333px]联系方式：15922980530（微信同号）

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You will bechallenged by the complexity and difficulty of designing/verifying the  high density memory chip (up to 16Gb) withhuge scale of circuit capability (over 4M transistors), ultra high speed (clockcycle is less than 1ns), complicated functionality (DDR4, LPDDR4), advanced lowpower and power management technology.

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You will need tohave the ability to work as a design verification engineer and consider as acircuit designer to full evaluate chip or block level functionality and providesolution.

• You will work closely with Micron's various design teams all over     the world to contribute to the success of the design team by applying verification     tools and techniques, providing verification status and summaries to     specific designs as needed.
• You may need to travel to Japan and U.S. in short term for     technical communication, project support.
• As part of a multi-disciplinary team, you will participate in     developing digital/Analog mix-signal verification methodology for advanced     DRAM products, as well as design and implementation of mix-signal design     verification environment.
• As an important part of responsibility, you will develop and maintain     test benches and test vectors using digital and analog simulation tools.

Responsibilities

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Build behavioral models in high-level with verilog/system-verilog/UVMlanguages, which can work at block level or whole chip level.

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Build coverage metrics for DRAM products based on external/internalspecifications.

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Develop new methodologies for DRAM verifications by using python/perl/C++languages, and be capable to do the second developments based on the 3rd vendortools.

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Develop patternsand regressions to increase the function coverage for all DRAM architecturesand features.

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Create newmethods and flows to guide DRAM chip design from verification view.

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Co-work withinternational colleagues on developing new verification tools and flows for theverification difficulties on DRAM chip.

Requirements

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[size=13.3333px]5+ years of experience incomplex IC verification and/or IC design preferred. Previous work experience inmemory related fields is a plus

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Experience infunction verification and timing analysis

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Experience in Verilog/SystemVerilog/UVMlanguages

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Good codingexperiences in Perl, Python, C, Shell and C++ is a plus

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Skilled inwriting function coverage metrics and SV assertion

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Strongcommunication skills with the ability to convey complex technical concepts toother verification peers both verbally and written

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The ability towork independently and in teams

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Highly motivatedand self-starter

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Multi-taskingability is a must

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Strong Englishskill in both writing and speaking is a must