ASIC RTL Design Engineer

KT咨询-IC电子

NO.487-【猎头职位：深圳需要五位 ASIC RTL Design Engineer】联系人：Raymond-Chen,邮箱：hr@kthr.com，微信也可查询职位了！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！

Job Description:

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Design RTL for our CPU-centric MachineLearning ASIC chip

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Optimize timing and power consumption

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Support functionality debug in simulation andemulation

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Write timing/power constraint for the design

Job Requirement:

MUST

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MS or PhD degree in Electrical Engineering,Computer Science, Physics, Mathematics or equivalent disciplines.

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MS with > 2 years of industrialexperience; more experiences and capability will correspond to higher joblevels.

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Excellent RTL design skills with SystemVerilog.

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Good scripting skills with Python/Perl/Tcl.

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Solid understanding of low power optimization.

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Proficient communication in English - bothorally and in writing form.

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Self-driven, result-oriented; able tomulti-task and determine priorities.

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A proven fast learner and a team player.

PREFERRED

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Knowledge and experience with RISC-V ISA ishighly desired.

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Knowledge about CPU architecture and memoryhierarchy.

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Experience of working with foreign coworkersand remote teams is a plus.

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