vhdlan 解析找不到unisim库 ？

american007

使用vhdlan -full64 -f filelist_vhdl.vhdl -y /EDA/xilinx_lib/unisim -l vhdl.log对vhdl文件进行解析，是否需要加库 -y /EDA/xilinx_lib/unisim？
出现如下提示：
Parsing design file '../../../../user/HDMI_SRC/HDMI_FPGA_ML_A7_0/src/TMDSEncoder.vhd'
Parsing design file '../../../../user/HDMI_SRC/HDMI_FPGA_ML_A7_0/src/SerializerN_1.vhd'

Error-[XSYMTABNOLIBMAP] Missing library map
  Library logical name 'UNISIM' is not mapped to a host directory.
  The show_setup command shows all of the mappings for the libraries.  Please
  use this command to validate that the named library above is mapped to a
  physical directory in your synopsys_sim.setup file.

七点班车

要在synopsys_sim.setup里加上：
unisim: $unisim_path/64,其中$unisim_path需要具体的路径

american007

感谢，vcs和vivado的版本 没有匹配造成的