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工作地点:上海,核心团队在美国,可以先去美国培训2~3个月时间
RTL Design Engineer
Required:
Experienced in RTL design
Experienced in designs involves complex clock domains
Strong in Perl, Python and tcl
Preferred:
Experienced in PLI routines
Experienced in RS FEC Encoder/Decoder
Experienced in Ethernet Packet Parser design
Familiar with Cadence design flow
3~5+ years industrial experience
DV Engineer
Required:
Experienced in System Verilog
Experienced in setting up verification flow
Experienced in creating regression flow using SQL database and Job queue
Strong in Make/Perl/tcl
Preferred:
Experienced in using PLI routines
Familiar with Cadence design flow
5~7+ years industrial experience
希望找入职快的,离职状态的最好,简历请发: sjtu_ee_2018@163.com |
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