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本帖最后由 小芯 于 2020-1-6 09:48 编辑
Position：
1.Design Implementation (Back End/Physical Design) Engineer / Sr. Engineer
2.DFT/Sr. DFT engineer
具体JD和公司介绍如下：
【Design Implementation (Back End/Physical Design) Engineer / Sr. Engineer】
-Responsibilities:
1. Responsible for SDC and UPF/CPF development and debug;
2. Focus on design floor planning, power planning, IO planning, placement & CTS and routing, handling timing and congestion issue during project implementation;
3. IP level and chip level physical verification and DFM rule checking;
4. Power analysis and IR drop/EM analysis for both static and dynamic;
5. Strong capability in timing analysis, and independently handle all timing issues from netlist/RTL to GDS process;
6. Responsible for timing signoff for all functional modes and concerns, and work closely with DFT engineer for scan modes timing closure;
7. Work closely with package team and IO team regarding IO placement to address IO ESD, SSO and chip power supplement concerns;
8. Communicate with customer as well as AE or sales.
-Requirements:
1. Bachelor’s degree or above in EE;
2. Skilled in csh/perl/tcl;
3. 2+ years work experience in relevant areas is required for Senior Engineer position;
4. Good knowledge in at least one of the following disciplines: high speed chip P&R skills, advance node chip P&R, hierarchical flow or low power P&R implementation, physical layout & verification;
5. Rich experience on timing/noise violation fixing and CTS tree synthesis;
6. Good understanding about entire development flow of IC design;
7. Good understanding about FE design, process, package, testing, etc;
8. Fluent in both English and Chinese
9. Self motivated, good communication skill and team work spirit.
【DFT/Sr. DFT engineer】
DFT engineer
-Responsibilities:
1.Be responsible for block/top level DFT implementation, DFT verification
2.Silicon bring up, pattern tuning
3.DFT flow development and benchmark
4.Support DFT timing closure and related design rule check
-Requirements：
1.BS or MS, major in EE or related discipline
2.Interest in IC design implementation and silicon test
3.Solid background on Verilog and ASIC design
4.Understanding on IEEE 1149/1500, Scan test plans and ATPG
5.Understanding on Memory BIST
6.Programming and scripting skills in Perl, or Tcl
7.Good teamwork spirit
8.Strong and continuous learning capability, self motivated
Sr. DFT engineer
-Responsibilities:
1.Be responsible for DFT implementation, verification, DFT structure and test plan definition
2.Silicon bring up, pattern tuning
3.DFT flow development and benchmark
4.Support DFT timing closure and related design rule check
5.Silicon debug and yield improvement
-Requirements：
1.Solid background on Verilog and ASIC design
2.Proven knowledge and expertise in defining and implementing IO test, Scan test plans and ATPG, understanding on Memory BIST, be familiar with Mentor/synopsys/Cadence EDA tools
3.Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
4.Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
5.Experience in silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing and diagnostics
6.Strong programming and scripting skills in Perl, or Tcl
7.Good communication capability and teamwork spirit
8.Strong and continues learning capability, self motivated
欢迎自投或推荐简历到 hr.resume@verisilicon.com
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发表于 2018-11-19 11:42:15
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