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本帖最后由 zhuyeyi 于 2018-11-7 13:49 编辑
RESPONSIBILITIES:
- Develop and execute verification plan
- Develop and maintain verification environment from unit level to system level
- Define and implement functional/code coverage plan
- Code/functional coverage analysis
- Responsible for running both RTL & gate level simulation
- Develop testing and regression methodologies for new verification flow
- Develop/maintain/enhance environment tools/scripts/makefiles
REQUIREMENTS:
- Proficient and experienced with the C/C++ program
- Experience in ASIC design or verification
- Proficient with Verilog HDL - Proficient with one or more scripting languages, such as Shell, Perl and TCL
- Familiar with logic simulators and debug tools (VCS, NC-Verilog, Verdi etc)
- Familiar with hardware verification language(Vera, Specman-E, SystemC, SystemVerilog), SystemVerilog is a strong plus
- Skill on Makefile is required
- Experience with Verilog PLI is a plus
- Master degree in Electrical Engineering/Computer
待遇优渥,16月年薪+股票。工作地点:南京
简历发至jing.lu@paradetech.com |
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