The phrase “CMOS scaling” is understood today to represent size reduction and performance enhancement of CMOS devices over time. In particular, this phrase is used to describe the evolution of devices fabricated using ever-moreadvanced CMOS process technology generations. Recent articles on CMOS scaling (e.g., Bohr [1]) highlight over four decades of increased miniaturization and improved performance for devices fabricated using over 20 CMOS process technology generations