Digital Design Rabaey 2nd edition

asic_ant

CONTENTS
PART I: THE FABRICS
Chapter 1: Introduction (32 pages)
1.1 A Historical Perspective
1.2 Issues in Digiital Integrated Circuit Design
1.3 Quality Metrics of a Digital Design
1.3.1 Cost of an Integrated Circuit
1.3.2 Functionality and Robustness
1.3.3 Performance
1.3.4 Power and Energy Consumption
1.4 Summary
1
DIGITAL INTEGRATED CIRCUITS
A DESIGN PERSPECTIVE
2 N D E D I T I O N
Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic
CONTENTS
PART I: THE FABRICS
Chapter 1: Introduction (32 pages)
1.1 A Historical Perspective
1.2 Issues in Digiital Integrated Circuit Design
1.3 Quality Metrics of a Digital Design
1.3.1 Cost of an Integrated Circuit
1.3.2 Functionality and Robustness
1.3.3 Performance
1.3.4 Power and Energy Consumption
1.4 Summary
2 CONTENTS
1.5 To Probe Further
1.6 Exercises
Chapter 2: The Manufacturing Process (30 pages)
2.1 Introduction
2.2 The CMOS Manufacturing Process
2.3 Design Rules — The Contract between Designer and Process Engineer
2.4 Packaging Integrated Circuits
2.5 Perspective — Trends in Process Technology
2.6 Summary
2.7 To Probe Further
2.8 Exercises and Design Problems
Design Methodology Insert A: Design Layout and Design Rule Verification (6 pages)
Chapter 3: The Devices (52 pages)
3.1 Introduction
3.2 The Diode
3.2.1 A First Glance at the Diode — The Depletion Region
3.2.2 Static Behavior
3.2.3 Dynamic, or Transient, Behavior
3.2.4 The Actual Diode—Secondary Effects
3.2.5 The SPICE Diode Model
3.3 The MOS(FET) Transistor
3.3.1 A First Glance at the Device
3.3.2 The MOS Transistor under Static Conditions
3.3.3 Dynamic Behavior
3.3.4 The Actual MOS Transistor—Some Secondary Effects
3.3.5 SPICE Models for the MOS Transistor
3.4 A Word on Process Variations
3.5 Perspective: Technology Scaling
3.6 Summary
3.7 To Probe Further
3.8 Exercises and Design Problems
Design Methodology Insert B: Device Models and Circuit Simulation (6 pages)
Chapter 4: The Wire (40 pages)
4.1 Introduction
4.2 A First Glance
4.3 Interconnect Parameters — Capacitance, Resistance, and Inductance
4.3.1 Capacitance
4.3.2 Resistance
4.3.3 Inductance
4.4 Electrical Wire Models
CONTENTS 3
4.4.1 The Ideal Wire
4.4.2 The Lumped Model
4.4.3 The Lumped RC model
4.4.4 The Distributed rc Line
4.4.5 The Transmission Line
4.5 SPICE Wire Models
4.5.1 Distributed rc Lines in SPICE
4.5.2 Transmission Line Models in SPICE
4.6 Perspective: A Look into the Future
4.7 Summary
4.8 To Probe Further
4.9 Exercises and Design Problems
PART II: A CIRCUIT PERSPECTIVE
Chapter 5: The Static CMOS Inverter (47 pages)
5.1 Introduction
5.2 The Static CMOS Inverter — An Intuitive Perspective
5.3 Evaluating the Robustness of the CMOS Inverter: The Static Behavior
5.3.1 Switching Threshold
5.3.2 Noise Margins
5.3.3 Robustness Revisited
5.4 Performance of CMOS Inverter: The Dynamic Behavior
5.4.1 Computing the Capacitances
5.4.2 Propagation Delay: First-Order Analysis
5.4.3 Propagation Delay Revisited
5.5 Power, Energy, and Energy-Delay
5.5.1 Dynamic Power Consumption
5.5.2 Static Consumption
5.5.3 Putting It All Together
5.5.4 Analyzing Power Consumption Using SPICE
5.6 Perspective: Technology Scaling and its Impact on the Inverter Metrics
5.7 Summary
5.8 To Probe Further
5.9 Exercises and Design Problems
Chapter 6: Designing Combinational Logic Gates in CMOS (64 pages)
6.1 Introduction
6.2 Static CMOS Design
6.2.1 Complementary CMOS
6.2.2 Ratioed Logic
6.2.3 Pass-Transistor Logic
6.3 Dynamic CMOS Design
6.3.1 Dynamic Logic: Basic Principles
6.3.2 Speed and Power Dissipation of Dynamic Logic
4 CONTENTS
6.3.3 Issues in Dynamic Design
6.3.4 Cascading Dynamic Gates
6.4 How to Choose a Logic Style?
6.5 Perspective: Gate Design in the Ultra Deep-Submicorn Era
6.6 Summary
6.7 To Probe Further
Design Methodology Insert C: Gate-Level Design and Analysis of Digital Circuits (10 pages)
Chapter 7: Designing Sequential Logic Circuits (46 pages)
7.1 Introduction
7.2 Timing Metrics for Sequential Circuits
7.3 Classification of Memory Elements
7.4 Static Latches and Registers
7.4.1 The Bistability Principle
7.4.2 SR Flip-Flops
7.4.3 Multiplexer-Based Latches
7.4.4 Master-Slave Based Edge Triggered Register
7.4.5 Non-ideal clock signals
7.4.6 Low-Voltage Static Latches
7.5 Dynamic Latches and Registers
7.5.1 Dynamic Transmission-Gate Based Edge-triggred Registers
7.5.2 C2MOS Dynamic Register: A Clock Skew Insensitive Approach
7.5.3 True Single-Phase Clocked Register (TSPCR)
7.6 Pulse Registers
7.7 Sense-Amplifier Based Registers (Consolidate with 7.6 under “other registers?”)
7.8 Pipelining: An approach to optimize sequential circuits
7.8.1 Latch- vs. Register-Based Pipelines
7.8.2 NORA-CMOS—A Logic Style for Pipelined Structures
7.9 Non-Bistable Sequential Circuits
7.9.1 The Schmitt Trigger
7.9.2 Monostable Sequential Circuits
7.9.3 Oscillators
7.10 Perspective: Choosing a Clocking Strategy
7.11 Summary
7.12 To Probe Further
7.13 Exercises and Design Problems
Design Methodology Insert D: Timing Analysis and Verification (8-10 pages)
Chapter 8: Dealing with Interconnect (45 pages)
8.1 Introduction
8.2 Capacitive Parasitics
8.2.1 Capacitance and Reliability—Cross Talk
8.2.2 Capacitance and Performance in CMOS
CONTENTS 5
8.3 Resistive Parasitics
8.3.1 Resistance and Reliability—Ohmic Voltage Drop
8.3.2 Electromigration
8.3.3 Resistance and Performance—RC Delay
8.4 Inductive Parasitics
8.4.1 Inductance and Reliability— Voltage Drop
8.4.2 Inductance and Performance—Transmission Line Effects
8.5 Perspective: When to Consider Interconnect Parasitics
8.6 Chapter Summary
8.7 To Probe Further
8.8 Exercises and Design Problems
Design Methodology Insert E: Interconnect modeling and analysis (6 pages)
PART III: A SYSTEM PERSPECTIVE
Chapter 9: Designing Complex Digital Integrated Circuits (40 pages)
9.1 Introduction
9.2 The Standard-cell Design Approach
9.3 Array-based Design
9.4 Configurable and Reconfigurable Design
9.5 Perspective: Facing the Increasing Design Complexity
9.6 Summary
9.7 To Probe Further
9.8 Exercises and Design Problems
Chapter 10: Timing Issues in Digital Circuits (55 pages)
10.1 Introduction - Classification of Timing Approaches
10.2 Synchronous systems
10.3. Impact of clock variation on performance
10.4. Clock Distribution Basics
10.5. Performance and Power Optimization in Synchronous Design
10.6. Asynchronous Design
10.7.The Asynchronous-synchronous Interface
10.8. Clock Signal Generation
10.9 Perspective: Alternative Synchronization Approaches
10.10 Summary
10.11 To Probe Further
10.12 Exercises and Design Problems
Chapter 11: Designing Arithmetic Building Blocks (50 pages)
9.1 Introduction
9.2 Datapaths in Digital Processor Architectures
9.3 The Adder
9.3.1 The Binary Adder: Definitions
6 CONTENTS
9.3.2 The Full Adder: Circuit Design Considerations
9.3.3 The Binary Adder: Logic Design Considerations
9.4 The Multiplier
9.4.1 The Multiplier: Definitions
9.4.2 The Array Multiplier
9.4.3 Other Multiplier Structures
9.5 The Shifter
9.5.1 Barrel Shifter
9.5.2 Logarithmic Shifter
9.6 Other Arithmetic Operators
9.7 Performance and Power Optimizations in Datapath Structures
9.8 Perspective: Design as a Trade-off
9.9 Summary
9.10 To Probe Further
9.11 Exercises and Design Problems
Chapter 12: Designing Memory Arrays (70 pages)
10.1 Introduction
10.2 Semiconductor Memories—An Introduction
10.2.1 Memory Classification
10.2.2 Memory Architectures and Building Blocks
10.3 The Memory Core
10.3.1 Read-Only Memories
10.3.2 Nonvolatile Read-Write Memories
10.3.3 Read-Write Memories (RAM)
10.4 Memory Peripheral Circuitry
10.4.1 The Address Decoders
10.4.2 Sense Amplifiers
10.4.3 Drivers/Buffers
10.4.4 Timing and Control
10.5 Memory Reliability and Yield
10.5.1 Signal-To-Noise Ratio
10.5.2 Memory yield
10.6 Case Studies in Memory Design
10.6.1 The Programmable Logic Array (PLA)
10.6.2 A 4 Mbit SRAM
10.7 Perspective: Semiconductor Memory Trends and Evolutions
10.8 Summary
10.9 To Probe Further
10.10 Exercises and Design Problems
Design Methodology Insert F: Chip Floorplanning (8 pages)
Chapter 13: Connecting to the Outside World (15-20 pages)
This also presents mostly new material. It addresses the following topics:
- pad design, ESD, guard rings, latchup
CONTENTS 7
- off-chip signaling: termination, current versus voltage mode,
high-speed serial links,
Design Methodology Insert G: Validation and Test of Manufactured Circuits (8 pages)
G.1 Test Procedure
G.2 Design for Testability
G.3 Test-Pattern Generation
Problem Solutions
Index

[ 本帖最后由 asic_ant 于 2007-11-6 20:05 编辑 ]

asic_ant

Digital Design Rabaey 2nd edition
Chapt1、Chapt2、Chapt3

[ 本帖最后由 asic_ant 于 2007-11-6 21:05 编辑 ]

asic_ant

Digital Design Rabaey 2nd edition
Chapt4、5、6

[ 本帖最后由 asic_ant 于 2007-11-6 21:03 编辑 ]

asic_ant

Digital Design Rabaey 2nd edition
Chapt7、10

[ 本帖最后由 asic_ant 于 2007-11-6 21:05 编辑 ]

nieyangboshi

Barrel shifter

denap

THanks for sharing!!

miles

全了吗?好像还有一章?

zhuxuxiaojie

:lol :lol

zhuxuxiaojie

zhuxuxiaojie

:o :o :o :o