Overview on Designs for Mixed-Voltage I/O Interfaces(IEEE 2006)

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS— REGULAR PAPERS, VOL. 53, NO. 2, FEBRUARY 2006

Overview on Electrostatic Discharge Protection
Designs for Mixed-Voltage I/O Interfaces: Design
Concept and Circuit Implementations

Ming-Dou Ker, Senior Member, IEEE, and Kun-Hsien Lin, Member, IEEE

Abstract—
Electrostatic discharge (ESD) protection design for
mixed-voltage I/O interfaces has been one of the key challenges of
system-on-a-chip (SOC) implementation in nano-scale CMOSprocesses.
The on-chip ESD protection circuit for mixed-voltage I/O
interfaces should meet the gate-oxide reliability constraints and
prevent the undesired leakage current paths. This paper presents
an overview on the design concept and circuit implementations
of the ESD protection designs for mixed-voltage I/O interfaces
without using the additional thick gate-oxide process. The ESD
design constraints in mixed-voltage I/O interfaces, the classification
and analysis of ESD protection designs for mixed-voltage
I/O interfaces, and the designs of high-voltage-tolerant power-rail
ESD clamp circuit are presented and discussed.

Index Terms—
Electrostatic discharge (ESD), ESD protection
design, gate-oxide reliability, high-voltage tolerant, mixed-voltage
I/O interfaces, power-rail ESD clamp circuit.

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