ESD for CMOS Integrated Circuits with Mixed-Voltage I/O Interfaces (SCI 2006)

semico_ljj

ESD Protection Design for CMOS Integrated Circuits
with Mixed-Voltage I/O Interfaces

Wei-Jen Chang
Institute of Electronics
National Chiao-Tung University
Hsinchu, Taiwan
eda.ee87@nctu.edu.tw

Ming-Dou Ker
Institute of Electronics
National Chiao-Tung University
Hsinchu, Taiwan
mdker@ieee.org

Abstract—
With consideration on the gate-oxide reliability, the
new ESD protection design with ESD bus for 1.2/2.5-V mixedvoltage
I/O interfaces is reported by using the new proposed
high-voltage-tolerant power-rail electrostatic discharge (ESD)
clamp circuit. This proposed power-rail ESD clamp circuit
with only 1.2-V low-voltage NMOS/ PMOS devices can be
operated under the 2.5-V input conditions without suffering
the gate-oxide reliability issue. The experimental results in a
0.13-􀈝m CMOS process have confirmed that the proposed
power-rail ESD clamp circuit has high human-body-model
(HBM) and machine-model (MM) ESD robustness and fast
turn-on speed. The proposed power-rail ESD clamp circuit is
an excellent ESD protection solution to the mixed-voltage I/O
interfaces.

Avalon

谢谢，楼主了

LAS.xs

kankan

alex_bai

semico_ljj

Ker!!

hahaT-MAC

谢谢楼主！

sawfish

Thanks!

sawfish

Gooooooooood

alex_bai

flyfeng

谢谢了!