On-Chip ESD Protection Strategies for RF Circuits in CMOS Technology(SCI 2007)

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On-Chip ESD Protection Strategies for RF Circuits
in CMOS Technology
Ming-Dou Ker and Yuan-Wen Hsiao

Nanoelectronics and Gigascale Systems Laboratory
Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan

Abstract
Electrostatic discharge (ESD) protection design for RF
circuits has been one of the key challenges to implement
RF ICs in CMOS technology. On-chip ESD protection
circuit at the RF I/O pads often cause unacceptable
degradation to RF circuits. In this paper, ESD protection
design considerations for RF circuits are addressed, and
on-chip ESD protection strategies for both narrow band
and broadband CMOS RF circuits are also presented and
discussed.


References
[1] S. Voldman, ESD: Circuits and Devices, John Wiley &
Sons (2006).
[2] S. Voldman, ESD: RF Technology and Circuits, John
Wiley & Sons (2006).
[3] C. Richier, P. Salome, G. Mabboux, I. Zaza, A. Juge, and
P. Mortini, EOS/ESD Symp., p. 251 (2000).
[4] M.-D. Ker and C.-M. Lee, IEEE International Symp.
Circuits and Systems, p. 297 (2003).
[5] K. Gong, H. Feng, R. Zhan, and A. Wang, IEEE Trans.
Microwave Theory and Techniques, vol. 50, no. 1, p. 393
(2002).
[6] B. Razavi, RF Microelectronics, p. 45 (1998).
[7] V. Chandrasekhar, C. Hung, Y. Ho, and K. Mayaram,
IEEE European Solid-State Circuits Conf., p. 347 (2002).
[8] M.-D. Ker, W.-Y. Lo, C.-M. Lee, C.-P. Chen, and H.-S.
Kao, IEEE Radio Frequency Integrated Circuits Symp.,
p.427 (2002).

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