transient-induced latchup in CMOS ICs under system-level ESD (期刊論文—SCI)

semico_ljj

論文名稱 Component-level measurement for transient-induced latchup in CMOS ICs under system-level ESD considerations

指導教授 Ming-Dou Ker

研究生 S.-F. Hsu

日期 2006 -  09 分類
A.期刊論文—SCI

期刊 Ming-Dou Ker and S.-F. Hsu, “Component-level measurement for transient-induced latchup in CMOS ICs under system-level ESD considerations,” IEEE Trans. on Device and Materials Reliability, vol. 6, no. 3, pp. 461-472, Sep. 2006.

摘要         To accurately evaluate the immunity of CMOS ICs against transient-induced latch-up (TLU) under the system-level electrostatic discharge (ESD) test for electromagnetic compatibility (EMC) regulation, an efficient component-level TLU measurement setup with bipolar (underdamped sinusoidal) trigger is developed in this paper. A current-blocking diode and a currentlimiting resistance, which are generally suggested to be used in the TLU measurement setup with bipolar trigger, are investigated for their impacts to both the bipolar trigger waveforms and the TLU immunity of the device under test (DUT). All the experimental results have been successfully verified with device simulation. Finally, a TLU measurement setup without a current-blocking diode but with a small current-limiting resistance, which can accurately evaluate the TLU immunity of CMOS ICs with neither overestimation nor electrical-over-stress damage to the DUT during the TLU test, is suggested. The suggested measurement setup has been verified with silicon-controlled-rectifier test structures and real circuitry (ring oscillator) fabricated in 0.25-μm CMOS technology.  

關鍵字 Holding voltage, latch-up, silicon-controlled
rectifier (SCR), system-level electrostatic discharge (ESD) test, transient-induced latch-up (TLU)

liuzhieetop

:victory:

orioncherry

不错的一篇文章。

NCTUGICE

感謝分享囉
下載來參考看看

xyzw

感謝分享

lihaiqi208

Holding voltage, latch-up, silicon-controlled

wangzhanfei001

XXX
XXX

libinggl

多谢楼主

qwer123asdf123

Thanks!

efong

THANK YOU