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Low-power wordline voltage generator for low-voltage flash memory
期刊
T.-M. Wang, Ming-Dou Ker, S. Yeh., and Y.-C. Chang “Low-power wordline voltage generator for low-voltage flash memory,” Proc. of the 13th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2006), Nice, France, Dec. 10 – 13, 2006, pp. 220-223.
摘要
Wordline voltage generating circuit with high speed active mode and low power standby mode is proposed. In the active mode, two different ring oscillators with high clock frequency (fCLK) 170MHz, and low clock frequency (fCLK) 25MHz which is also the operating frequency of the entire circuit, are employed. The proposed circuit has a short response time of 3μs typically in active mode, and very low standby current about 3μA in standby mode.
[ 本帖最后由 semico_ljj 于 2007-9-28 11:36 编辑 ] |
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