Synopsys 招聘(社招、实习)，武汉，北京，上海

547420883

ASIC/Layout Design Engr         

Job Description and Requirements

                                                   

Must have 0-2 years experience in hands on layout development. Fresh engineers should be trained in analog layout and have a good grasp of layout concepts.
Must be able to work under guidance and able to run and debug tools and reports.
​knowledge of custom compiler is an added advantage.

Analog Design Engr

Job Description and Requirements

In this role, you will be responsible for designing, developing, troubleshooting, analyzing quality and debugging embedded memory compilers.

Requirements:

• Requires a minimum of a BSEE and 5 years of industry related experience.
• Must have sound CMOS design fundamentals.
• Experience in Design Margining and reliability.
• Have worked on Timing/Power/Leakage Optimization Techniques in the past.
• Exposure to Backend Design.
• Knowledgeable about basic scripting and tools such as simulation tool < hsim/hspice>, schematic and layout editor.
• Senior circuit design capabilities:
  • transistor level circuit design
  • some memory design experience will be a plus

Responsibilities:

Learns to use professional concepts. Applies company policies and procedures to resolve routine issues.

Follows standard practices and specific, outlined and detailed procedures in analyzing situations or data from which answers can be readily obtained.

Normally receives detailed instructions on work, which is reviewed regularly by manager or more senior peers.

Builds routine working relationships internally.

Contacts are primarily with direct manager and other peers in the group or department.




Intern (Technical-Engineering)The focus of work would be FPGA-Implementation/Embedded-SW (Driver software) in one of the following areas related to connectivity protocols:
USB/Ethernet/SDMMC/MIPI/Memory Controllers


感兴趣的私聊留言，发工作邮箱，非诚勿扰。

               

547420883

自己顶一波。
新思科技职位内推 ： base 北京 上海 武汉。
不吹不黑，待遇一流。