AI研发公司北京上海成都芯片设计后端全定制DFT等职位招聘

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北京 上海  成都等  AI公司职位

1.Physical Design- 在北京/上海

2.IC设计工程师芯片架构和安全算法方向  办公地点：北京/成都

3.IC设计工程师TPU/GPU/CPU任一方向都可以，及DDR方向、PCIE方向。办公地点：北京/上海

4.ASIC Flow：北京或者上海

5.全定制芯片工程师   北京

6.嵌入式开发  北京

7.高性能计算工程师  北京/上海

职位名称 ：芯片设计   

岗位职责

1. Participate in RISCV or Deep Learning Accelerator or other SOC IP design for all frontend phase

2. Specification define

3. RTL implementation

4. Analysis and optimization for performance

5. Analysis and optimization for power

6. Analysis and optimization for timing

7. Design flow: lint/synthesis/sta/formal check

8. Silicon debugging

任职条件

1. MS with 5+ or 3+ years of experience in ASIC design

2. Experience with RISC CPU (RISCV/MIPS/ARM) related IPs design are highly desirable

3. Experience with USB/MIPI_CSI/MIPI_DSI or other high speed interface IPs design are highly desirable

4. Experience with Deep Learning Accelerator related IPs design are highly desirable

5. Experience with all phases of frontend architecture, design and validation

6. RTL Coding, design reviews, SYN, CDC, FEV

7. Demonstrated work experience with timing analysis, area and power optimizations, performance analysis, debug ability, ECOs, and post-silicon debug

8. Excellent knowledge of Verilog and popular EDA simulation & implementation tools

9. Good experience in scripting languages like Perl, Unix shell or similar languages

全定制芯片设计工程师

职位概述

岗位职责

High performance, low power, small area custom digital circuit design for processors·

Circuit architecting, simulation and characterization of custom design circuit.                           

1. Transistor level function verification.

2. Participating in building CAD flow for circuit design.

3. Layout floor planning and supervision.

任职条件

1. BSEE minimum, MSEE preferredwith 1-5 years of working experience;

2. Strong background in deep submicron CMOS process and device.

3. Good knowledge in high speed digitalcircuit design techniques.

4. Experience in circuit simulation, schematic capture and layout verification CAD tools.

5. Must be a team player with effective written and verbal communication skills.

6. Quick learner and work independently.

DFT工程师：

Job description

Perform and/or lead various DFT tasks for the creation of SOC chips. The main areas of focus will be to architect, develop and optimize structured test solutions using DFT insertion and ATPG tools as well as BIST for memories, etc. He will be responsible for architecting and integrating DFT structures into RTL and netlists to deliver reliable, efficient and high quality manufacturing test coverage.

Key Responsibilities:

• Architect DFT strategies for complex SOC designs

• Generate and insert Scan, Memory BIST, Boundary Scan, Test Compression etc.

• Generate ATPG vectors for stuck-at, delay fault and other types

• Determine, analyze and enhance fault coverage to achieve target test quality

• Interface with ATE test engineer

Requirements:

•BS/MS in Electrical or Computer Engineering with 5+ years’related experience designing DFT for SOCs

•Expert level knowledge of DFT including scan, boundary scan, BIST, fault models and ATPG

•Strong working knowledge of SOC design and design methodology

•Skill and efficiency in scripting using common UNIX scripting languages such as TCL, Perl, csh

•Excellent RTL and gate level debug skills

•Strong experience with Verilog RTL design and simulation

•Desirable: Previous use/experience with ATE

•Desirable: Formal analysis / STA Experience

Asic后端设计工程师

RESPONSIBILITIES:

- Execute the whole Backend Design flow include Floorplan/Placement/CTS/Routing/Physical Verification

- Work with front end design Engineers to achieve timing closure for both partition level and full chip level

- IO ring design

- Cross talk Analysis

- IR Drop and Power Integrity Analysis

- Execute ECO's.

- Develop and enhance entire physical design flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.

MINIMUM REQUIREMENTS:

BS or MS in Electrical Engineering or Computer Science

Relevant ASIC experience ideally with a focus in the chip integration /synthesis/formal and timing closure

Excellent scripts skills

Keep up to date with leading edge technologies

Work under pressure