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Job Tasks:
Working with back-end on block and full-chip implementation, including floorplanning, synthesis, timing closure and sign-off
RTL2GATE formal check
Low power design and verification
Implementation flow development
Qualifications:
MSEE/MSCS Degree or equivalent
3-5 years' work experience in front-end ASIC implementation and design
Strong understanding of synthesis flow using Design Compiler or Genus
Strong STA skills, must have thorough knowledge on closing timing at block and top level
Hands on experience on formal verification using Formality/LEC
Experience on low power design flow and methodology
Ability to build new EDA-methodology-flow using Perl, Python, Tcl
Good communication skill and excellent team player |
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