CMOS Single Chip Fast Frequency Synthesizers For Wireless Applications

summerwaww

CMOS Single Chip Fast Frequency Hopping Synthesizers For Wireless Multi-Gigahertz Applications

summerwaww

CMOS Single Chip Fast Frequency Hopping Synthesizers For Wireless Multi-Gigahertz Applications

Contents
Preface ix
Nomenclature xi
1 INTRODUCTION
1.2 Research Contribution
2 WIRELESS COMMUNICATION SYSTEMS
2.1 Introduction
2.2 The WLAN Standards
2.3 WLAN Transceiver Systems
2.3.1 The Transmitter
2.3.2 The Receiver
2.3.3 The Frequency Synthesizer (Local Oscillator)
3 PHASE-LOCKED LOOP FREQUENCY SYNTHESIZERS
3.1 Introduction
3.2.1 Phase-Locked Loop Main Blocks
3.2.1.1 Phase-Frequency Detector
3.2.1.2 Charge Pump
3.2.1.3 Voltage-Controlled Oscillator
3.2.1.4 Voltage-Controlled Crystal Oscillator
3.3.1 Loop Filter Design
3.4.1 Component Noise Models
3.4.1.1 Reference Oscillator and VCO Phase Noise
3.4.1.2 Charge Pump Current Noise
3.4.1.3 Loop Filter Resistor Noise
3.4.1.4 Main Divider Noise
3.4.1.5 Phase-Frequency Detector Phase Noise
3.4.1.6 Overall Phase Noise Contribution
3.5 Fractional-N Synthesizers
3.5.1 􀀧􀀐􀀶 Modulators in Frequency Synthesizers
3.5.1.1 Fractional-N Case Study
3.7 Conclusion
4.1 Introduction
4.2.1 A Constituent Blocks Behavioral Models
4.2.1.1 The Reference Oscillator
4.2.1.2 The Modulator/Feedback Integer Divider
4.2.1.3 The VCO
4.2.1.4 The PFD/CP
4.2.1.5 The Loop Filter
4.2.2 Noise Modeling Summary
4.3 Synthesizer Platform Evaluation
4.3.1 Dithering Effect
4.3.2 Close-to-Integer Operation
4.3.3 Noise Folding
4.3.4 Effect of Prescaler Divider
5
5.1 Introduction
5.2 An overview
5.3.1 Design Methodology
5.4.1 The Phase-Frequency Detector
5.4.2 The Charge Pump
5.4.2.2 Linear Range and Cycle Slipping
3.4 Noise in Phase-Locked Loops 27
31
SYNTHESIZERS
4.2 Phase-Domain Model
5.3 A Multimode Multistandard 􀀧􀀐􀀶-Based PLL Synthesizer Design
5.4 The 􀀧􀀐􀀶 Frequency Synthesizer SubBlocks Implementation
5.4.2.1 Dead-Zone Nonlinearity
3.6 RMS Phase Error (􀁉rms) and Error Vector Magnitude
4 SYSTEM SIMULATION OF 􀀧􀀐􀀶-BASED FRACTIONAL-N
MULTIMODE 􀀧–􀀶-BASED FRACTIONAL-N FREQUENCY
5.4.2.3 DC Offset Current
5.4.2.4 PFD/CP Transient Simulation
5.4.4 The Multimodulus Divider
5.4.4.1 MMD Operation
5.4.5 The Fractional Noise Shaping Coder (the 􀀧􀀐􀀶 Modulator)
5.4.5.1 The Digital Accumulator and the First-Order Linear Model
5.4.5.2 The 30-bit Structural MASH Coder Implementation
5.4.5.3 The 24-bit Pipelined Adder Design
5.4.5.4 Error Cancellation Algorithm
5.4.5.5 Design Issues: Limit Cycle Cancellation in Fractional Mode
5.4.5.6 Design Issue: Integer Mode and Close-to-Integer Option
5.5 Measured Performance of the Implemented Synthesizer
5.6 Summary and Conclusion
6 IMPROVED PERFORMANCE FRACTIONAL-N FREQUENCY
6.1 Introduction
6.2 Overview
6.3.1 PLL Gain and Phase Variations
6.3.2 Charge Pump System
6.4 Synthesizer Loop Calibration
6.5 Process Calibration I/C Slew Rate and RC Time Constant
6.6.1 VCO Calibration Algorithm Description
6.6.1.1 􀀧N Values
6.6.1.2 Summary of Tuning Algorithm Operation
6.7 Improved VCO Band Switching
6.8 Experimental Results
6.9 Comparison with Published Results
6.10 Conclusion
7 CONCLUSION AND FURTHER WORK
7.1 Conclusion
7.2 Further Work
3 PFD/CP Characteristics
6.3 Delta–Sigma-Controlled Adaptive Charge Pump
6.6 VCO Tuning Gain Calibration
1 Phase-Frequency Detectors
2 Charge Pump
5.4.3 3.6 GHz Voltage-Controlled Oscillator

summerwaww

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summerwaww

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meowy

真是不錯的參考 感謝您的分享

pedro888

thanks for your information........
thanks.......

fanjx

有了  路过

worldjoker

看看，是好东西就要顶

worldjoker

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:victory:

gambolrf

谢谢分享