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楼主: 504472832

[资料] 分享Cadence XCELIUMMAIN_18.03.001

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发表于 2018-9-21 20:40:00 | 显示全部楼层
多谢多谢
发表于 2018-9-23 06:56:54 | 显示全部楼层
本帖最后由 sigurd 于 2018-9-23 07:11 编辑

Thank You!! Wait for happy version...
发表于 2018-9-25 19:57:29 | 显示全部楼层
no crack, how to use it?
发表于 2018-10-11 10:33:13 | 显示全部楼层
thank you for sharing
发表于 2018-10-28 23:32:20 | 显示全部楼层
many thanks .
发表于 2018-11-14 18:56:19 | 显示全部楼层
thanks for sharing
发表于 2018-11-18 22:23:18 | 显示全部楼层
Dose anybody have crack for sharing? Thank you very much.
发表于 2019-3-23 10:31:03 | 显示全部楼层
版本比你新点,18.09 run: 18.09-s010: (c) Copyright 1995-2019 Cadence Design Systems, Inc.
file: dut_dummy.v
        module worklib.dut_dummy:v
                errors: 0, warnings: 0
                Caching library 'worklib' ....... Done
        Elaborating the design hierarchy (primary partition):
xmelab: *N,MEVCON: In multi-run MSIE mode, explicit connectivity access from command-line would be required for tran gate pins, if '$dumpports' is used in the design.
        Top level design units:
                dut_dummy
xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
        Building instance overlay tables: .................... Done
        Generating native compiled code:
                worklib.dut_dummy:v <0x0ca9ca81>
                        streams:  17, words:  9380
        Building instance specific data structures.
        Loading native compiled code:     .................... Done
        Design hierarchy summary:
                         Instances  Unique
                Modules:         1       1
                Registers:       6       6
                Scalar wires:   71       -
                Always blocks:   3       3
        Writing primary snapshot: worklib.dut_dummy:v
xrun: 18.09-s010: (c) Copyright 1995-2019 Cadence Design Systems, Inc.
Compiling UVM packages (uvm_pkg.sv cdns_uvm_pkg.sv) using uvmhome location /tools/cadence/XCELIUM1809/tools/methodology/UVM/CDNS-1.1d
file: ubus_tb_top.sv
        package worklib.ubus_pkg:sv
                errors: 0, warnings: 0
        interface worklib.ubus_if:sv
                errors: 0, warnings: 0
        module worklib.ubus_tb_top:sv
                errors: 0, warnings: 0
Loading primary snapshot worklib.dut_dummy:v .................... Done
                Caching library 'worklib' ....... Done
        Elaborating the design hierarchy (incremental partition):
xmelab: *N,MEVCON: In multi-run MSIE mode, explicit connectivity access from command-line would be required for tran gate pins, if '$dumpports' is used in the design.
        [MSIE] Instance ubus_tb_top.dut is bound to module worklib.dut_dummy:v in primary snapshot worklib.dut_dummy:v
        Top level design units (incremental partition):
                uvm_pkg
                cdns_uvmapi
发表于 2019-4-5 19:05:27 | 显示全部楼层

好东西,拿走看看
发表于 2019-4-18 15:51:13 | 显示全部楼层


zw1035961900 发表于 2019-3-23 10:31
版本比你新点,18.09 run: 18.09-s010: (c) Copyright 1995-2019 Cadence Design Systems, Inc.
file: dut_ ...


可以分享一下Lic么 感谢!
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