one paper on JSSC 2007:A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 6, JUNE 2007

A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13-m CMOS Technology

Abstract—A 37–38.5-GHz clock generator is presented in this
paper. An eight-phase voltage-controlled oscillator (VCO) is
presented to generate the multiphase outputs. The high-pass characteristic
ladder topology sustains the high-frequency signals.
The split-load divider is presented to extend the input frequency
range. The proposed PD improves the static phase error and enhances
the gain. To verify the function of each block and modify
the operation frequency, two additional testing components—an
eight-phase VCO and a split-load frequency divider—are fabricated
using 0.13- m CMOS technology. The measured quadrature-
phase outputs of VCO and input sensitivity of the divider are
presented. This clock generator has been fabricated with 0.13- m
CMOS technology. The measured rms clock jitter is 0.24 ps at
38 GHz while consuming 51.6 mW without buffers from a 1.2-V
supply. The measured phase noise is 97.55 dBc/Hz at 1-MHz
offset frequency.

Index Terms—Clock generator, phase-locked loop (PLL).

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