This document details the typical steps of a top-down digital Vhdl/verilog design flow withthe help of one simple design example. The following tools, running in a Linux environment,are considered in this document: • Modelsim from Mentor Graphics.
• Design Compiler from Synopsys.
• Encounter and virtuoso from Cadence Design Systems.
The design kit used is the UMC
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90nm CMOS process with the Faraday standard cell library.