关于IC616 Spice in 的symbol的问题

pkji345

我最近在导入cdl网表成原理图的时候，因为很多是Global VDD和VSS，所以输入输出一左一右刚好。但是我想将VDD VSS设为非全局信号，想让VDD在symbol的上方，VSS在symbol的下方。我再导入的时候发现了一个地方是能调的。就是Schematic Generation里面的Pin Pleacement。我试过Left and Right Sides和All Sides，都不行，应该是需要写Pin Pleacement File，但是我上网查了，完全没有相应的格式可以参考，所以想问有大神知道该怎么写吗？

pkji345

人工顶

pkji345

人工顶

pkji345

1111111111111111111

账户已登录

几个月过去了还没有结论吗

claire123456

请问标准单元库导入schematic的时候如何生成symbol

jzr1989

Cadence自带帮助文档里有



Pin Placement

Specifies the placement of pins on a symbol. Pin placement can be defined as any of the following two options:


Left and Right Sides: Places pins on the left and right sides of a symbol, usually with input pins on the left and inout pins and output pins on the right.

All Sides: Places pins on any side of a symbol.

Pin Placement File: Places pins on specific sides of modules as defined in a file called pin placement file. When you select this option, you must provide the path of the pin placement file in the Pin Placement File Name field.
Pins and their placement on modules are defined in the pin placement file in the following format:
pin_placement := {moduleName, {left|right|top|bottom},comma-separated-pin-name-list}
For example:
pin_placement := inv, left,a,b,c,d
pin_placement := inv, top,e,f
pin_placement := test4, bottom, c, d
pin_placement := test4, left, e
The first line in the example given above specifies that module inv has pins a, b, c, and d oriented on the left side.
Default value: Left and Right Sides