AMD内部推荐岗位（内部推荐成功率高）

ab23com

有兴趣的同学，可以将简历发到ab23com@163.com

1.ASIC/ Layout Design Engineer - PD  

RESPONSIBILITIES:

• Understand the architecture of the graphics IP and     functional block being designed
• Build C/C++ model for simulation
• Build test bench and monitors for DUT
• Compose test plan and validation vectors to ensure     functional completeness
• Debug function/performance bugs of graphics IP
• Work with global Front-End design team and physical     design team for large scale ASIC chip physical implementation
• Focus on physical design of deep sub-micron GPU chips     including block level (full chip) floor planning, timing closure,     place&route, physical verification etc

REQUIREMENTS:

• Have in depth knowledge of entire design process from     Design specification, defining architecture, micro-architecture, RTL     design and functional verification, synthesis, Physical Design, Timing     closure, Tape-out, and post-Si debug.
• Have hands-on experience in Chiplevel     Design/Integration activities.
• Some Physical Design exposure required.
• Perform Synthesis and netlisting tasks such as SDC     Development, Scan Insertion, ECO implementation, Formal Verification, etc.
• Some exposure to DFT is a strong plus.
• Work with Physical Design team on Floor Plan,     budgeting, timing closure, Signal Integrity, ECO flows, Power analysis, IO     PAD placement, etc.
• Should have expertise in: Cadence RTL Compiler, Design     Compiler, PrimeTime, Conformal LEC. Good knowledge of datapath compilers     is required.
• Expertise in Perl and Tcl is a must.
• Knowledge of chip bus interfaces such as AHB and     various standard peripherals & interfaces is a plus.
• Should be able to work closely with RTL Designers and     Backend Physical Design teams across multiple sites.
• Must have good communication & Analytical thinking     skills.
• Should have proficiency in flow development and     scripting.
• 
  

EDUCATION:

• Master with at least 2 years or Bachelor with at least     4 years working experience in ASIC area

2. ASIC Layout Design Engineer - Feint (DC Synthesis, ICC P&R)

RESPONSIBILITIES:

• Understand the architecture of the graphics IP and     functional block being designed
• Build C/C++ model for simulation
• Build test bench and monitors for DUT
• Compose test plan and validation vectors to ensure     functional completeness
• Debug function/performance bugs of graphics IP
• Work with global Front-End design team and physical     design team for large scale ASIC chip physical implementation
• Focus on physical design of deep sub-micron GPU chips     including block level (full chip) floor planning, timing closure,     place&route, physical verification etc

REQUIREMENTS:

• Have in depth knowledge of entire design process from     Design specification, defining architecture, micro-architecture, RTL design     and functional verification, synthesis, Physical Design, Timing closure,     Tape-out, and post-Si debug.
• Have hands-on experience in Chiplevel     Design/Integration activities.
• Some Physical Design exposure required.
• Perform Synthesis and netlisting tasks such as SDC     Development, Scan Insertion, ECO implementation, Formal Verification, etc.
• Some exposure to DFT is a strong plus.
• Work with Physical Design team on Floor Plan,     budgeting, timing closure, Signal Integrity, ECO flows, Power analysis, IO     PAD placement, etc.
• Should have expertise in: Cadence RTL Compiler, Design     Compiler, PrimeTime, Conformal LEC. Good knowledge of datapath compilers     is required.
• Expertise in Perl and Tcl is a must.
• Knowledge of chip bus interfaces such as AHB and     various standard peripherals & interfaces is a plus.
• Should be able to work closely with RTL Designers and     Backend Physical Design teams across multiple sites.
• Must have good communication & Analytical thinking     skills.
• Should have proficiency in flow development and     scripting.
• 
  

EDUCATION:

• Master with at least 2 years or Bachelor with at least     4 years working experience in ASIC area

3.ASIC/ Layout Design Engineer - DV

Job Responsibilities:

*Subsystem/IP level test plan development

*Work with architecture/IP designers to get a full deep insight on the designunder test

*Subsystem level test bench build, verification component build

Education& Qualifications:

     Candidate is preferred to be MSEE withminimum of 2 years, or BSEE with minimum of 4-year experience in digitalASIC/SOC design verification.

Experience:       1. Complex IP/ASIC/SOC Design Verification, direct  experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard  (PCI-e, HT) is preferred.    2. Good knowledge of UVM    3. Good knowledge of Verilog/C/C++/System  C/SystemVerilog.    4. Verification insights into random techniques.    5. Experience of verification lead is an asset.    6. Experience of PCIe verification is an asset.    7. Experience in power verification is an asset.    8. Verification of Virtualization is an asset.    9. Strong C and C++ software development and scripting  languages (Perl, C Shell, Makefile, …) experience.    10. Solid background with hardware verification  methodologies such as coverage-based verification methodology with the use of  hardware assertions (PSL or SVA).

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4. ASIC/Layout Design Engineer - DFT

RESPONSIBILITIES:

• Understand the architecture of the graphics IP and     functional block being designed
• Build C/C++ model for simulation
• Build test bench and monitors for DUT
• Compose test plan and validation vectors to ensure     functional completeness
• Debug function/performance bugs of graphics IP
• Work with global Front-End design team and physical     design team for large scale ASIC chip physical implementation
• Focus on physical design of deep sub-micron GPU chips     including block level (full chip) floor planning, timing closure,     place&route, physical verification etc

REQUIREMENTS:

• Have in depth knowledge of entire design process from     Design specification, defining architecture, micro-architecture, RTL     design and functional verification, synthesis, Physical Design, Timing     closure, Tape-out, and post-Si debug.
• Have hands-on experience in Chiplevel     Design/Integration activities.
• Some Physical Design exposure required.
• Perform Synthesis and netlisting tasks such as SDC     Development, Scan Insertion, ECO implementation, Formal Verification, etc.
• Some exposure to DFT is a strong plus.
• Work with Physical Design team on Floor Plan,     budgeting, timing closure, Signal Integrity, ECO flows, Power analysis, IO     PAD placement, etc.
• Should have expertise in: Cadence RTL Compiler, Design     Compiler, PrimeTime, Conformal LEC. Good knowledge of datapath compilers     is required.
• Expertise in Perl and Tcl is a must.
• Knowledge of chip bus interfaces such as AHB and     various standard peripherals & interfaces is a plus.
• Should be able to work closely with RTL Designers and     Backend Physical Design teams across multiple sites.
• Must have good communication & Analytical thinking     skills.
• Should have proficiency in flow development and     scripting.
• Should be able to Lead a team, and provide Technical     mentoring and guidance to junior engineers.

EDUCATION:

• Master with at least 2 years or Bachelor with at least     4 years working experience in ASIC area

5.Machine/ Deep Learning Software engineer

Job description

We are now looking for a Machine/Deep Learning Software Development Engineer:

What You’ll Be Doing But Not Limited

• Responsible for AMD Machine/Deep Learning Software Development (Driver, SDK, Frameworks);
• Develop testing for Machine/Deep Learning products to ensure functionality, compatibility and performance;
• Performance/Power Analysis,  Optimization, Tuning of Deep Learning Kernels
• Triage, isolate failures of root cause analysis and work with global development team to verify fixes;

What We Need To See

• BS or higher degree in CS/EE/CE or equivalent;
• Strong programming skills in C or C++
• Excellent communicator, both written and verbal;
• Scripting language (Python, Perl ) knowledge and UNIX/Linux experience is required;

Ways To Stand Out From The Crowd

• Driver development experiment is a good Plus
• OpenCL/CUDA/C++ Amp/ROCm/Compiler development experience is  a strong Plus
• Familiarity working with GPU hardware is a strong plus;

    *   Familiarity any Deep Learning framework is a strong plus;