求書:Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current Reduction

Capricorn0115

求書ow-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current ReductionAuthor:P. van der Meer, A. van Staveren, Arthur H.M. van Roermund

1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase. In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance.

ohyesdcy

回复 1# Capricorn0115
Low-Power Deep Sub-Micron CMOS Logic.pdf (6.59 MB, 下载次数: 260 )

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im.leo

多谢分享

lhyi

Thank you

amigo.change

Capricorn0115

回复 2# ohyesdcy

Thank you~

student321

Low-Power Deep Sub-Micron CMOS Logic.pdf (6.59 MB)

xuleiwx

谢谢分享

Minibaby

这个很实用，是的一看

cdting

非常感謝~~~~