马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
大家好，GlobalFoundries中国设计中心(原IBM芯片设计中心)招聘各类IC工程师，如果你对技术感兴趣，可以将简历投递到：taozhang3260@163.com职位列表 Backend Design Engineer Memory Design Engineer Memory Layout Design Engineer Memory BIST Logic Design Engineer Package Design Engineer Senior Staff Account manager Senior Staff Engineer Field Engineering (RF/Digital)（技术支持） Senior Staff Engineer Field Engineering (Analog/Digital)（技术支持）
Backend Design Engineer
Description ●
Physical design methodology development and enhancement for leading edge technologies of ASIC, including floor planning, placement, design opt, clocking, routing, power opt, timing closure, physical verification, etc. ●
Enable design team for design flow flush, trouble-shooting, QoR improvement, and chip completeness. ●
Support design team for implementation of requests for special design flow/methodology customization of productivity enhancement. ●
Develop on-demand minor flow for design optimization and PD/timing closure. ●
System-level design flow qualification with world-wide methodology team.
Qualifications ●
3-5 years of experience in the following areas: ●
Physical/timing experience in ASIC design, development experience of high volume and high reliability ASIC chips in customer products. ●
Strong background in digital ASIC design preferably in networking and switching chips. ●
Strong expertise of ASIC physical implementation flow: floorplanning, power planning, top-down/bottom-up flow, placement/opt/routing, power consumption optimization, and design closure. ●
Strong expertise of scripting and design automation of design jobs. ●
Excellent written and verbal communication skills and solid teamwork and leadership skills. ●
Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation. ●
Working knowledge of TCL/TK, Perl/Python, Shell script, C/C++ language.
Memory Design Engineer
Location: Shanghai/Beijing, China
Responsibilities: GLOBALFOUNDRIES Memory Design Engineer is working on cutting-edge embedded Memory IP development for GLOBALFOUNDRIES worldwide clients, including SRAM, RF, TCAM, ROM, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies including 14nm and beyond, you will be participating in: ● Design full custom circuits in the embedded memory arrays ● Simulate, verify and analyze memory functionality, performance and statistical margin ● Perform functional verification, characterization and model-to-hardware correlation ● Evaluate and optimize memory architecture and methodology in cutting-edge technology
Requirements:
1. ME/EE or background in related areas 2. Experience in one or more of the following embedded or standalone memory products/circuits: SRAM, DRAM, Flash, Register File, TCAM, ROM, etc 3. Familiar with transistor level circuit EDA tools (Virtuoso, Spectre, HSPICE, etc.) 4. Good understanding of advanced semiconductor technology process and device physics 5. Experience with statistical circuit analysis and simulation is a plus 6. Good English skills, communication skills, and willingness to work with a global team. Skill in other languages is a plus 7. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment
Memory Layout Design Engineer
Location: Shanghai/Beijing, China
Responsibilities:
GLOBALFOUNDRIES Layout Design Engineers at are responsible for circuit layouts development for our industry-leading IP offerings, including SerDes, memory, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor cutting-edge technologies ranging from 14nm and beyond, the layout design engineer is responsible of the floor planning, physical design and verification.
Requirements: 1. BS and above in Electrical or Related areas 2. Good understanding of advanced semiconductor technology process and device physics 3. Full-custom circuit layout/verification and RC extraction experience. Experiences in one or more of following areais preferable · Mixed signal/analog/high speed layout, eg SerDes,ADC/DAC, PLL etc · High performance/capacity memory layout, eg SRAM, RF, RA, etc 4. Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC, LVS, DFM, etc.) 5. Experiences in advanced technology node under 32nm/28nm/16nm/14nm and FinFET is preferable 6. Experiences with EMIR analysis, ESD, antenna and related layout solutions is preferable 7. Good English skills, communication skills, and willingness to work with a global team 8. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.
Memory BIST Logic Design Engineer
Location: Shanghai, China
Responsibilities: GLOBALFOUNDRIES BIST Logic Engineer is working on cutting-edge Memory IP BIST development. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies on 7nm and beyond, you will be participating in the BIST design and verification, including architecture definition, logic design, and block and system level module verification.
Requirements: 1. ME/EE/CS or background in related areas, with 3+ years industry experience 2. Skilled in RTL logic design (Verilog and/or VHDL), research and/or development skill in one or more of the following area is preferable: BIST, ATPG, DFT, UVM Verification 3. Proficiency in programming and/or scripting languages 4. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment 5. Good English skills, communication skills, and willingness to work with a global team
Package Design Engineer
Description GLOBALFOUNDRIES Package Design Engineer is responsible for large scale ASIC package definition, package model extraction, system-module SI/PI co-simulation and thermal/reliability solution. Support ASIC chip designs on IO planning based on GLOBALFOUNDRIES 32nm, 14nm and beyond technology. Design of high-speed package escape patterns and power delivery structures. Manage ASIC package laminate design from definition to manufacture. Explore advanced package solutions such as 2.5D, 3D package. Development of tools in support of image/package/PCB co-design.
Work scope includes but not limited to: ●
Package solution consulting and evaluation during project bid stage ●
Define package netlist based on chip-package co-design methodology ●
IO planning together with physical designer ●
Package ERC checking, package design file checking ●
Support customer on system-module SI/PI co-simulation ●
Package design sign-off ●
Develop package design methodology in China Design Center ●
Develop advanced 2.5D, 3D package design solution
The candidate would also have future extended responsibility participating in the design planning and sizing for the advanced ASIC/SoC chips, deployment and other application engineering support of the design methodology.
Qualifications 1.
EE/ME/CS related background in system/chip design 2.
Solid knowledge and extensive industry experience in one or more of the following areas: ○
High speed package/system design experience (High Speed Serdes, HBM, DDR, etc...) ○
Familiar with Industry SI/PI analysis process, system level modeling and finite element analysis tools (Ansys HSFF, Sigrity, SigXp, Spice, MATLAB, etc...) ○
Multiple layers PCB/Laminate (4+) layout experience (Experience with automation, such as cadence APD and related design tools, and SKILL language programming is a plus) 3.
Good grasp of Perl/TCL scripts under Linux/Unix environment. C programming will be a plus. 4.
Good communication skill in both English and Mandarin, and willingness to work with a global team. Skill in other languages is a plus. 5.
Understanding of ASIC physical design process/tools, advanced semiconductor technology process and device physics is a plus 6.
Strong teamwork sense, good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment. 7.
Direct package engineer role with industry experience
Senior Staff Account manager
Manage existing customer accounts and establish new customer base Establish and manage channel business development relationship Forecast monthly/quarterly/annual business volumes Provide feedback on competitive product price trends in target markets Work with engineering to provide the best solutions to meet customers’ requirements Ensure effective implementation of business development activities in each target market. Facilitates communication between customers and Fab to ensure all business requirements are met in areas of product performance information, and evaluates design requirements to determine whether they fit with GLOBALFOUNDRIES capabilities Negotiate business terms and agreements with customer accounts Lead and mentor his team to achieve GLOBALFOUNDRIES’s business objectives Issuing Quotations to customer Take ownership of RW to customer Take ownership of RTP to customer Take ownership for issuing BX008 with review by FE Obtaining reticle quotations from vendors with verified reticle set by FE Making technical presentations to potential and existing customers by having assistance from FE Work closely with FEs, Customer Service Representatives, and Administration as a team to communicate information and maximize GLOBALFOUNDRIES customer satisfaction
Degree in Electrical or Electronics Engineering, with post-graduate Degree in Business preferred Minimum 10 years of working experience and at least 5 years in similar job capacity Goal/target oriented Proven track record in sales Strong desire to achieve customer satisfaction Good interpersonal skills
Senior Staff Engineer Field Engineering
Description:
The GLOBALFOUNDRIES Design and Technology Support team is responsible for providing direct technical support on Design Enablement tools and Technologies to customers engaged in designing integrated circuits in GLOBALFOUNDRIES's state-of-the-art RF SiGe, RF CSOI, High Voltage and CMOS technologies. In addition to answering specific questions for the customers, the team also provides technical training. The team is also responsible to drive client requests and insight into the internal development teams, resulting in increased competitiveness in the marketplace and higher client satisfaction. Experience with industry standard RFIC simulation, design checking and parasitic extraction tools such as Cadence, Mentor and Synopsys DRC, LVS and PEX, and/or silicon technology development is required. Problem identification and debugging skills are used heavily.
Job Requirements:
1. Master/Ph.D with EE, Microelectronics or Computer Engineering related background. 2. Industry experience (5 years) in related RF/digital circuit design, semiconductor technology/process development or CAD/Industry Design Tools Application areas. 3. Good Knowledge in one or more of the following semiconductor industry related fields: - Advanced semiconductor technology processing in BCD, SiGe, BiCMOS, CSOI, HV or Bulk CMOS. - High Performance RF/Analog, Digital/SOC Custom and Mixed-Signal Circuit design, simulation, verification, testing and evaluation. - CAD/Industry Design Tools Development or Application experience. 4. Knowledge/Experience in one or more of the following application domains, will be a plus: - Communication and wireless applications - Digital media, audio/video applications - Consumer electronics applications - Automotive electronics applications - Other emerging technology and industry areas 5. Fluent English; Good communication and problem solving skills and willingness to work within a global team. 6. Good learning competency, self-motivation, and be able to work on diverse areas in a flexible environment. 7. Strong technical leadership will be important consideration for senior positions.
Senior Staff Engineer Field Engineering
Field Application Engineering is responsible for understanding customer's business and organization. Has familiarity with customer's system product roadmap, technology requirements, development environment and applicable industry standards. Also to understands broader market directions and competitive trends.
He (She) acts to understand GLOBALFOUNDRIES Microelectronics strategy and alliances to know GLOBALFOUNDRIES Microelectronics organization, processes, technical resources as well as key Factory contacts within Business Line and Development organizations. Represents entire GLOBALFOUNDRIES Microelectronics product portfolio to customers, and provide specialized technical support within own product discipline.
1. Master/Ph.D with EE, Microelectronics or Computer Engineering related background. 2. Min 5 years of relevant experience in Semicon industry) in related design, semiconductor technology/process development or CAD/Industry Design Tools Application areas. 3. Good Knowledge in one or more of the following semiconductor industry related fields: - Advanced Semiconductor Technology/Processing/Modeling: SiGe, Bulk CMOS, BiCMOS, SOI or technologies. - High-Performance RF/Analog, Digital/SOC Custom and Mixed-Signal Circuit design, simulation, verification, testing, and evaluation. - CAD/Industry Design Tools Development or Application experience. - Electrostatic Discharges (ESD) protection design. 4. Knowledge/Experience in one or more of the following application domains will be a plus: - Communication and wireless applications - Digital media, audio/video applications - Consumer electronics applications - Automotive electronics applications - Other emerging technology and industry areas 5. English fluent, Good communication/Problem-Solving skill and willingness to work within a global team. 6. Good learning competency, self-motivation, and be able to work on diverse areas in a flexible environment. 7. Strong technical leadership will be an important consideration for senior positions. | 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2017-12-9 22:22:19
发表于 2017-12-26 17:20:30