virtuoso转出CDL(spice Netlist)出现问题

bridgepons

我想自己画一个电路图,然后在virtuoso里面依据我画出的电路图,来画IC Layout

我已经服务器里面放置了想关tf drf drc的档案,就欠一章电路图~~

所以我使用cadence里面的composer-schematic 这个功能来画电路~

我使用symbol是virtuoso里面的analogLib叫出来的~~

后来我画完有check and save , 接着要Export 出 CDL

但出现failed.....后来我查询了一下

出现底下错误:

Running Artist Hierarchical Netlisting ...

ERROR: Netlister: unable to descend into any of the views defined in theview

list: "auCdl schematic" for instance I10 in celllayout_example.

Either add one of these views to: Library: analogLib Cell: dummy ormodify

the view list to contain an existing view.

End netlisting Dec  3 10:48:552017

ERROR (OSSHNL): Error(s) found during netlisting. The netlist may becorrupt

or may not be produced at all.

To generate correct netlist, fix the errors and re-netlist.

啊~~可是我的电路图没使用I10的组件啊~~~

eetop的版友...谁可以帮帮我啊~~

   谢谢 ~~~~~

KatyChiang

I10 是啥cell呀？可不可以skip掉？

yhp2008

I10是自动生成网络标号，无法生成cdl，有可能是自带库的ipin、 opin、 in 、out有问题，删除就可以生成cdl